Analog Layout Engineer

Join Apples Silicon Engineering Group (SEG) and be at the forefront of shaping the next generation of Apples systems-on-chip (SOCs)! Our SOCs featuring multi-billion transistors are the heart of iconic devices like iPhones iPads and Macs. Were seeking highly skilled Analog Layout engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits covering SerDes PLLs and an Analog Layout engineer youll play a crucial role in translating design concepts into silicon collaborating closely with circuit designers and leveraging advanced tools. Your work will involve creating custom analog designs to optimize the performance of Apples world-class this dynamic and innovative environment youll have endless learning opportunities while collaborating across dedicated multidisciplinary job is right for you if you are a self-motivated engineer passionate about working with cutting-edge technology. You want to accelerate career growth thrive in a results-oriented environment and contribute to the development of revolutionary Apple products. The roles include crafting upcoming products challenging oneself and broadening skillsets in a dynamic innovative work culture!

Analog Layout engineers are pivotal in delivering Analog Mixed-Signal IP in a SOC flow. You will collaborate with teams of highly skilled individuals to develop the next generation of world-leading SOCs. Your responsibilities include crafting sophisticated layouts for mixed-signal and analog circuits reviewing floorplans and analyzing intricate circuits with circuit designers. Youll run complete sets of design verification tools plan/schedule work and coordinate vital layout tradeoffs. Interpretation of LVS DRC and ERC reports is key to finding the fastest way to complete the layout exceeding engineering specifications and expectations.

BS and a minimum of 10 years relevant industry experience.

10 years of experience in analog/mixed-signal layout design with a focus on deep submicron CMOS circuits and at least 3 years in FinFET knowledge in SKILL Perl TCL Shell and/or with Machine Learning and AI with ultra-high speed ADC/DAC. nnProven Expertise in implementing analog layout designs achieving tight matching low noise and low power consumption. nnMust recognize failure-prone circuit and layout structures have experience with analog and DFM standards and be able to identify the best approach to solving Proficiency in custom and standard cell-based floor-planning and hierarchical layout understanding of IR drop RC delay electromigration self-heating and coupling Proficiency in interpreting physical verification reports (DRC ERC LVS etc.).nnExperience using Cadence Virtuosos advanced features (XL EAD APR and Constraint Manager).nnExcellent communication skills and ability to work with cross-functional Automation creation or Ph.D. in Electrical and Computer Engineering.