IC Package Design Engineer

Our Packaging team defines designs and integrates advanced electronic packaging solutions for Apples internal and custom components across products including iPhone iPad Mac Apple Watch and Apple TV. Were looking for a Package Design Engineer to drive the physical design and integration of advanced semiconductor packages across SoC memory RF and cellular technologies. You will play a key role in shaping the architecture scalability and efficiency of next-generation products while advancing design methodologies through automation and AI.

As a Package design engineer you will lead advanced package architecture drive next-generation package structure and configuration optimization and own Package/SiP/module physical design from concept through tape-out. You will collaborate closely with cross-functional teams to deliver optimized SI/PI performance across a wide range of silicon technologies You are expected to leverage AI tools to enhance design efficiency quality and performance.

Perform physical layout of package substrates for diverse silicon including System-on-Chip (SoC) Memory RF and cellular integrated circuits (ICs).nExecute parasitic extraction (RLGC) and S-parameter modeling to validate that package designs meet Signal and Power Integrity (SI/PI) performance cross-functional collaboration on package feasibility and system co-optimization; align with Product Design on chip floorplan System Architecture on package configuration and Silicon/SIPI teams on electrical package design methodology improvements by evaluating new CAD tools and developing automated design and verification flows to enhance efficiency and streamline the release process.

Bachelors degree required.

Package Design Proficiency: Proven experience in IC package physical design using Cadence Allegro or Mentor Xpedition platforms with knowledge of diverse package types (SiP PoP wirebond) and verification tools (Calibre CAM350).nHigh-Speed u0026 SI/PI Expertise: Strong understanding of high-speed interface layout constraints (DDR PCIe) and Signal/Power Integrity (SI/PI) analysis including experience with simulation tools like HFSS or PowerSI and parasitic extraction (RLGC S-parameters).nManufacturing u0026 Materials Knowledge: Solid grasp of substrate manufacturing processes design rules (DRC) design for manufacturability (DFM) and various sophisticated package configurations and assembly technologynAutomation u0026 Scripting Skills: Familiarity with a Unix/Linux environment and proficiency in scripting languages such as Python Perl or TCL to automate design tasks and improve workflows.