Senior 3D MEMS and Test Development Engineer

• Test Strategy & Equipment Setup:Define and deploy the test infrastructure required to characterize 3D MEMS process steps thermal bonding wafer-level packaging TGV electrochemical or mechanical reliability testing. Specify qualify and operate metrology electrical test and reliability equipment.
• Process Characterization & DOEs:Design and execute structured experiments to characterize 3D MEMS unit processes and integrated flows. Generate the data needed to set process windows control limits and acceptance criteria across coupled process steps.
• Data Analysis & Industrialization:Build Python-based data pipelines to analyze high-volume process and test data. Extract yield Cpk drift and failure-mode signatures. Translate findings directly into process and test recipe improvements.
• Hardware & Electrical Characterization: Lead electrical and physical characterization across 3D MEMS structures. Use SMUs DAQs oscilloscopes probe stations and dedicated MEMS test rigs to measure critical parameters at the required precision.
• Materials & Failure Analysis: Apply materials science fluency thin films interfaces integration physics to root-cause analysis on failures across bonding packaging TGV interfaces and electromechanical reliability. Feed findings back to process and design teams to drive iterations.
• Cross-Functional Coordination: Work directly with Process Integration Packaging Hardware mechanical and Software teams to align test requirements hardware specifications and data infrastructure. Translate 3D MEMS physics into testable specifications across disciplines.
• Industrialization & Scaling: Take prototype test setups out of R&D and harden them for pilot and production. Author SOPs qualify equipment (IQ / OQ / PQ) and integrate with MES where applicable.
• Continuous Improvement: Identify opportunities to reduce variation improve test throughput and tighten the link between process control and electrical / yield outcomes across the 3D MEMS stack.
  
  

• Bachelors or Masters degree in Electrical Engineering Applied Physics Materials Science Microelectronics or a related field.
• 5 years in Test Development Device Characterization or Yield Engineering within a semiconductor MEMS or advanced packaging environment.
• Vertical Integration & MEMS Expertise: Hands-on experience with testing and characterizing advanced packaging architectures including wafer-level thermal bonding Through-Glass Vias (TGV) / TSV metallization and electromechanical reliability.
• Data Science & Scripting: High proficiency in Python (e.g. Pandas NumPy SciPy) for complex data analysis instrument control (SCPI/VISA) and automating high-volume lot-level data workflows.
• Test Equipment & Instrumentation: Hands-on expertise building test setups with SMUs DAQs oscilloscopes and automated metrology tools. Highly capable of debugging signal integrity for low-noise/high-impedance analog measurements.
• Physics of Failure: Deep understanding of semiconductor/MEMS device physics thin films and electromechanical integration. Must understand why an interface fails (e.g. CTE mismatch delamination voiding) to design accurate test traps.
• Industrialization Track Record:Proven ability to take prototype test platforms out of R&D and industrialize them for pilot or production use including authoring SOPs and executing equipment qualification (IQ/OQ/PQ).
• Systematic first-principles approach to problem-solving.
• A strong instinct for identifying R&D fragility.
• Strong written and verbal communication.
• Takes full ownership of test strategy equipment readiness and data quality.
• Thrives in fast-moving unstructured deep-tech environments.

• Database Architecture:Experience interfacing automated test hardware with Manufacturing Execution Systems (MES) or SQL databases and building visual dashboards (e.g. Grafana PowerBI) for tracking yield and Cpk.
• Reliability & Environmental Testing:Practical knowledge of accelerated aging models hermeticity testing (leak rate analysis) and Electrochemical Impedance Spectroscopy (EIS).
• Neurotechnology & Mixed-Signal Electronics:Familiarity with high-channel-count analog front-ends (AFEs) custom ASICs or complex neural electrophysiology signal chains.
• Statistical Process Control:Working knowledge of PFMEA DOE methodology SPC and Cpk-driven process control in regulated manufacturing environments.
• Pilot-to-Production Scaling:Prior experience supporting a deep-tech hardware company through a pilot-to-production transition including capital tooling and scale-up decisions.

WHAT CAN WE OFFER TO YOU

• Acollaborative environment where innovative ideas flourish and teamwork drives us forward. At INBRAIN we believe the power of collective intelligence is unique. You will be part of a team that thrives on open communication knowledge sharing and mutual respect.
• Meaningful Work Impact:Our projects are not only exciting and challenging but also have a positive impact on the industry and society as a whole. Youll be part of a team that strives to create meaningful change.
• Cutting-Edge Technology Exposure:Joining us means immersing yourself in the latest technologies and innovative solutions. Youll have access to state-of-the-art tools and resources fostering continuous learning and keeping your skills relevant in a rapidly evolving industry.
• Competitive salary (according to your experience/skills)
• Internal flexible compensation scheme
• Private Health Insurance
• Training bonus for professional development and access to Udemy platform
• 23 vacation days per year
• Christmas week off
• While we offer flexible working modality because of the nature of this position this will be an office-based position in Bellaterra.