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Verification Engineer 4- #26-22322
Job Location:
Job Location:
Austin, TX - USA
Hourly Salary:
USD 70 - 80
Hourly Salary:
Posted:
22 October 2026 (Yesterday)
Posted:
Application Deadline:
19 January 2027
Application Deadline:
Vacancies:
1 Vacancy
Vacancies:
Job Summary
Duration: 12 months
Job Description
- Hands-on experience with VC Formal (Synopsys) and/or Jasper Gold (Cadence)
- Strong proficiency in System Verilog Assertions (SVA) and formal property specification
- Experience with formal verification applications: FPV connectivity checking register verification equivalence checking and coverage analysis
- Familiarity with scripting languages (TCL Python Perl) for flow automation
- Extensive experience in design verification with a strong focus on formal verification
- Expertise in System Verilog and UVM-based verification methodologies - Nice to have
About US Tech Solutions:
US Tech Solutions is a global staff augmentation firm providing a wide range of talent on-demand and total workforce solutions. To know more about US Tech Solutions please visit .
US Tech Solutions is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race colour religion sex sexual orientation gender identity national origin disability or status as a protected veteran.
AI Statement: By applying you acknowledge that AI-assisted tools may be used during hiring.
Required Experience:
IC
About Company
USTECH SOLUTIONS is the largest independent diversity workforce partner operating a global footprint. For 20+ years, we have partnered with leading MSPs and some of the world’s largest enterprises to deliver a flexible workforce.
