Validation CAD Engineer

Do you love creating elegant solutions to highly complex challenges Do you intrinsically see the importance in every detail As part of our Silicon Technologies group youll help design and manufacture our next-generation high-performance power-efficient processor system-on-chip (SoC). Youll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by this group means youll be responsible for crafting and building the technology that fuels Apples devices. Together you and your team will enable our customers to do all the things they love with their devices! In the CAD organization you will get to create new software and technologies that will enable other Apple engineers create products for millions of customers across the world.n

Formal Verification CAD engineering plays a major role in promoting a reliable work environment for Formal Verification teams. There are many applications within the formal verification arena that need support and development such as formal property checking low power connectivity checks sequential equivalence checking (SEC) and coverage. As member of our CAD team you will develop maintain and enhance the flows that our internal teams use to create the next generation of Apple addition to maintaining and enhancing our Formal Verification flow the position offers a large variety of opportunities ranging from detailed application profiling and tuning to development of Continuous Integration/Deployment pipelines to large scale compute cluster management. You will have the opportunity to integrate your ideas and add new features to the system as well as collaborate with other CAD teams in various functional front-end areas.n

You will be responsible for developing maintaining and enhancing an existing system of executing a formal verification tooln You will help out with supporting our existing Jasper reset analysis SEC and formal proofing flowsn You will utilize your debugging experience to debug vendor tool problems and interact with designers/formal verification team to help solve their problemsn

Experience scripting in Python Perl Kotlin or TCLnExperience in Software Development with Test in-mindnKnowledge in Verilog and System VerilognMinimum requirement of BS and 3 years of relevant industry experience

Familiarity with Jasper or VC Formal products is highly desirablenExperience in formal verification is a plusnPrior customer support experience is a plusnExperience with DevOps flows is a plus nComfortable with co-developing an existing system