Staff Engineer, PCIe PHYLink Analysis

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What Youll Do

• Protocol Stack Analysis: Understand PHY/Link architecture implementation and integration of the PCIe protocol stack from the Physical Layer through the Data Link Layer to the Transaction/Transport Layer in collaboration with internal H/W teams and external vendors.
• Link Bring-up & Training: Own LTSSM behavior link training and equalization sequencing PCIe enumeration and configuration-space flows during device bring-up.
• Transaction/Transport Layer: Analyze and validate TLP/DLLP handling flow control credit management ordering rules ACK/NAK and replay error handling (AER) and end-to-end data integrity across the stack.
• Debug & Optimization: Analyze and debug complex PHY Link and Transport layer issues during bring-up and sustaining stages of NVMe SSD products from Gen1 to the latest generation (Gen7) covering protocol (LTSSM / PCIe enumeration) and PCIe feature-related issues.
• Compliance & Standards: Participate in and support industry PHY/Link compliance tests including PCI-SIG events.
• Field Support: Provide onsite support for PHY/Link related tasks at customer sites and labs.
• Travel: This position requires up to 25% business travel.

What You Bring

• BS in Computer/Electrical/Electronic Engineering or Computer Science and 8 years of relevant experience in hardware or a MS in Computer/Electrical/Electronic Engineering or Computer Science with 5 years of relevant experience is required.
• Protocol Expertise: Deep proficiency with the PCIe protocol spanning the entire architecture from the Physical Layer through the Data Link Layer to the Transaction/Transport Layer.
• Link Layer Mastery: Strong hands-on knowledge of LTSSM link training/equalization PCIe enumeration flow control replay/retry and error handling (AER).
• PHY Awareness: Working knowledge of PHY-layer operation (CDR to Equalizer such as VGA CTLE DFE FFE DSP etc ) sufficient to root-cause link issues that cross the PHY/Link boundary.
• Firmware & Debugging: Solid experience in C/C for embedded systems and expertise with UART/JTAG/ICE debuggers and general firmware debugging techniques.
• Analysis Tools: Strong experience with PCIe protocol analyzers logic analyzers and signal analyzers for link and transaction-level debug.
• Collaboration: Ability to work effectively within a multi-functional team environment.

Preferred Skills

• Knowledge on SI/PI for PCIe
• Extended Protocols: Proficiency in NVMe CXL or SAS/SATA protocols is a significant plus.
• Validation: Experience in both pre-silicon and post-silicon SoC validation.
• Power Management: Experience with PCIe power management (ASPM L1 substates) and low-power link states.

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