Solutions Engineer, AI for Chip Design
California, CA - USA
Job Summary
This is a full-time on-site position for a Solutions Engineer AI for Chip Design based in San Jose this role you will:
Deploy agentic AI systems into real semiconductor design engineering workflows
Work directly with leading semiconductor companies to understand design workflows identify high-value pain points define success metrics and validate impact
Collaborate closely with AI researchers EDA researchers infrastructure engineers and chip design experts to solve challenging design problems
Turn ambiguous customer problems into working prototypes production deployments and reusable product capabilities
Design evaluations analyze failures debug workflows and improve agent systems through real-world feedback
Build polished technical demos customer-facing slides and compelling proof-of-value presentations
Independently prototype and rig together quick demos to show what is possible before a full product or engineering team is available
Anticipate customer needs across verification RTL physical design and custom design and proactively build toward future applications
Move fast learn constantly and own technical outcomes end-to-end
As a Solutions Engineer you will help shape both the product direction and the future workflows of AI-native chip development. This is a hands-on customer-facing technical role for someone who combines chip design depth AI curiosity strong communication and startup-level execution.
We are looking for someone who has:
BS/MS degree in Computer Engineering Computer Science Electrical Engineering or a related field
3 years of chip design experience in at least one of the following areas: design verification RTL design physical design or custom design
Strong technical credibility with semiconductor engineering teams with the ability to speak peer-to-peer with design verification CAD and EDA engineers
Familiarity with generative AI systems agentic workflows or multi-agent architectures
Comfortable working directly with customers including understanding requirements presenting technical ideas and handling open-ended technical discussions
Strong problem-solving ability in messy real-world engineering environments
High energy adaptability curiosity and willingness to learn quickly
Excellent verbal and written communication skills
Ability to thrive in a fast-moving highly collaborative startup environment
You will stand out if you have:
Experience across multiple parts of the chip design stack especially RTL design design verification and physical design
Built or deployed agentic AI systems for real chip design EDA or semiconductor engineering workflows
Developed innovative chip design methodologies EDA algorithms design automation scripts or internal productivity tools
Strong software development and systems skills with the ability to quickly build prototypes connect tools automate flows and create working demos
A strong customer presence: outgoing engaging confident and comfortable presenting to senior engineering teams
Ability to create polished impressive demo slides and deliver them clearly
A scrappy self-sufficient working style able to make progress without waiting for perfect infrastructure or a large support team
A speculative product-oriented mindset able to anticipate customer pain points and imagine new applications before customers fully articulate them
Published work in chip design EDA AI for hardware or related technical areas
Experience working in startup-like environments where speed ownership and ambiguity are part of the job
The ideal candidate is a technically deep chip design engineer who is excited about AI enjoys working with customers and can translate real semiconductor pain points into working agentic solutions.
You should be credible enough to engage directly with experienced customer engineering teams energetic enough to lead demos and workshops and scrappy enough to build prototypes independently. You are not only reacting to customer requests you are actively thinking ahead about where agentic AI can transform chip design workflows.