SoC Physical Design Verification Engineer
Austin, TX - USA
Job Summary
As a member of our physical design team you will perform various types of physical verification checks (such as LVS DRC design-for-manufacturing u0026 design-for-yield and lithography) at the chip and block level.n You will collaborate with the CAD/Technology teams for flow bring up and validation. We work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout.n You will lead schedules and support cross-functional engineering efforts.n You will work on padring bump RDL design and working with the package and floorplan teams.
BS and 10 years of relevant industry experience.
Experienced with physical verification flows such as DRC/LVS/ANT/HVDRC signoff flows and full-chip integration methodologynExperience with ESD and macro placement design guidelines digital and analog mixed signal back-end verification checks and methodology nKnowledge of all aspects of ASIC physical design and physical verification checks for hierarchical designs including full-chip flowsnScripting skills perl/python/tcl to debug flow related issues and automate checksnExperienced in industry standard tools used for physical verification such as Mentor Calibre Synopsys ICV experience with a track record of successful signoffsnLayout design experience is a plus
Required Experience:
IC
About Company
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