SoC Physical Design Methodology Engineer

At Apple we work every single day to craft products that enrich peoples lives! Do you love creating elegant solutions to highly complex challenges Do you intrinsically see the importance in every detail As part of our Silicon Technologies group youll help design and manufacture our next-generation high-performance power-efficient processor system-on-chip (SoC). Youll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining our group means youll be responsible for crafting and building the technology that fuels Apples devices. Together we will enable our customers to do all the things they love with their devices! In this highly visible role you will be a part of a critical team responsible for physical verification of an SOC.

As a member of our physical design team you will perform various types of physical verification checks (such as LVS DRC design-for-manufacturing u0026 design-for-yield and lithography) at the chip and block level.n You will collaborate with the CAD/Technology teams for flow bring up and validation. We work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout.n You will lead schedules and support cross-functional engineering efforts.n You will work on padring bump RDL design and working with the package and floorplan teams.

BS and 10 years of relevant industry experience.

Experienced with physical verification flows such as DRC/LVS/ANT/HVDRC signoff flows and full-chip integration methodologynExperience with ESD and macro placement design guidelines digital and analog mixed signal back-end verification checks and methodology nKnowledge of all aspects of ASIC physical design and physical verification checks for hierarchical designs including full-chip flowsnScripting skills perl/python/tcl to debug flow related issues and automate checksnExperienced in industry standard tools used for physical verification such as Mentor Calibre Synopsys ICV experience with a track record of successful signoffsnLayout design experience is a plus