SOC Design Verification Engineer

Apples wireless chip powers connectivity across every new iPhone and its successor is already taking shape. Would you like to join Apples growing wireless silicon development team Our wireless SOC organization owns every aspect of wireless silicon development with a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level. It is driven by a world-class vertically integrated team spanning RF/Analog Systems/PHY/MAC VLSI/RTL design and integration Emulation Design Verification Test and Validation and FW/SW engineering. As a Wireless SOC Design Verification Engineer youll be at the heart of the chip design effort owning a meaningful verification scope and growing it project to project.

Youll be responsible for pre-silicon RTL verification at the block subsystem and top-level SOC taking your scope from test planning through coverage closure and signoff. Working closely with architects designers and firmware engineers youll build reusable testbenches and verification environments using modern metric-driven methodology. Areas you may work on include the Power Management Unit CPU subsystem DMA on-chip debug infrastructure PCIe bus fabric boot and secure-boot sequencing MAC-PHY Verification Radio integration and peripherals such as SPI choosing simulation formal or whichever approach the design actually calls for. Low power is part of your scope wherever it shows up: youll verify power intent using UPF within your time you can grow deeper into the IPs and subsystems you know best or broader across IPs and up from block level to full SOC integration. The team is also pushing hard on AI-assisted verification and youll help figure out where it fits best: test generation debug coverage closure or all the above.

Partner with architects and designers early to build detailed verification plans from specifications before RTL lands not reusable block/IP and subsystem-level UVM testbenches and support IP integration into the directed and constrained-random tests; create and analyze coverage models and drive coverage failures including corner cases and manage bug tracking through low-power design intent using UPF within your end-to-end WiFi and Bluetooth traffic flows from subsystem level up through top-level SOC formal verification where it fits the team will help you ramp and improve automated regression flows and contribute to methodology in your and apply AI-assisted verification techniques to improve team in verification reviews and uphold high coding-quality post-silicon bring-up as needed.

Minimum requirement of a bachelors -on experience across the verification cycle: test planning testbench implementation test creation and debug and coverage SystemVerilog and Verilog skills with solid working knowledge of problem-solving and debugging skills with constrained-random of digital logic design SOC architecture and microarchitecture.

Experience taking at least one ASIC/SOC from concept through experience with PCIe bus fabric/NOC or AHB/AXI-based architectures in a UVM verifying IP or top-level integration for a WiFi or Bluetooth SOC or knowledge of wireless with low-power verification UPF boot-up power-cycling and HW/FW with SystemVerilog Assertions (SVA) and/or formal tools (e.g. JasperGold).nExperience defining coverage space and writing coverage with embedded CPU verification; programming in C/C or in Python or Perl; interest in applying AI/ML to verification workflowsnGreat teammate with excellent communication skills and the desire to take on diverse challenges.