SerDes Design and Validation Engineer

Apple is looking for a SerDes Design and Validation Engineer to Lead system validation of mixed-signal SerDes this highly visible role you will contribute to the design integration and validation of high-performance analog and mixed-signal circuits for SerDes PHY applications. This encompasses the design and optimization of critical building blocks such as receivers transmitters bias generators high-speed clock generation and distribution networks targeting best-in-class power performance and area metrics. A key part of your design responsibilities will include the development of analog DFT circuits and techniques essential for comprehensive PHY validation. You will develop test plans review and analyze data to guarantee a robust IP design. You will drive and work closely with production test (e.g. ATE system validation) teams and debug complex design and system bring-up issues. At Apple we strive every day to create products that enrich peoples lives a mission that brings exciting challenges in SOC/PHY design! Were looking for individuals with strong fundamentals and a proven track record to tackle complex technical problems. You are driven by curiosity eager to learn new skills and motivated to maximize the impact of your work. You see the big picture while diving deeply into details to innovate and solve problems. You thrive in collaborative diverse teams maintaining a positive spirit even when challenges arise. Above all you care about making a difference in society and demonstrate leadership through meaningful contributions. We have an opportunity for a forward-thinking and especially hardworking system validation engineer with strong background in high-speed serial links. As a member of our dynamic team you will have the rare and rewarding opportunity to work on upcoming products that will surprise and delight millions of Apples customers every day. And all of this while enjoying a great culture where you own your career.

In this role the key responsibilities are the following: Ownership of SerDes system bring-up validation and debug. This will involve a SerDes bring up in system environment verifying basic operations analyzing robustness and margins in system. Work with design teams to understand the architecture and define DFT needs to help enhance testability and first-time silicon success. Be involved in mixed-signal verification tasks to better understand the SerDes operation and interaction with higher level control logic.

BS and a minimum of 10 years relevant industry experience.

The ideal candidate should have experience in high-speed serial links with expertise in the following:nSolid understanding and experience of designing analog mixed signal circuit blocks including Bandgap biasing circuits LDO regulators amplifiers comparators switched-cap circuits ADCs DACs Oscillators understanding of analog mixed-signal concepts like mismatch mitigation linearity stability low-power and low-noise understanding and experience with digitally assisted analog design concepts (e.g. background calibrations LMS based adaptive loops).nHands-on experience to drive lab and production testing debug and data analysis nHands-on experience with AMS IC development from definition to high-volume production including layout supervision bench evaluation correlation and in scripting and automation to enhance efficiency are highly in high-speed serial links with knowledge of common high-speed SerDes protocols like PCIe USB DP and of Tx/Rx equalization techniques and circuits including CTLE DFE and de-emphasis as well as CDR architectures and of common high-speed SerDes protocols (e.g. PCIe USB DP MPHY) is highly to firmware assisted mixed signal IP development is desirable. nKnowledge and inquisitiveness in AI/ML domains and ability to apply the concepts for improved silicon performance and also for productivity improvements in the design/validation of the IP