Senior FPGA Signal Processing Engineer

Position Title:Senior FPGA Signal Processing Engineer
Requisition ID: 1871
Position Location:Fairfax VA
Position Reports To:Senior Manager FPGA Engineering
Supervises Others:No

At Trident Systems Space Electronic Systems (SES) division we believe in the power of using strong engineering principles to drive innovation and solve complex problems. We foster a culture of rigorous engineering and continuous improvement leveraging the full knowledge of our organization through collaborative product development processes that include design and peer reviews. We combine our expertise in space electronics with right-sized development processes to create innovative high-performance space-based electronic systems that meet our customers evolving needs.

We are a mission partner supporting DoD Intelligence Community and Civil space customers. We develop complex radiation effects mitigated designs that balance competing requirements in modern space programs delivering cutting-edge solutions that enable our customers to achieve more in space.

Position Summary

The Senior FPGA Signal Processing Engineer (Image/Video and Compression) will play a critical role in the design and development of advanced FPGA-based imaging and data compression solutions supporting space-based electronic systems. This position is responsible for architecting implementing and verifying complex high-speed programmable logic designs for systems that process analyze and compress image and video data.

The ideal candidate brings strong expertise in image and video processing and compression algorithms with the ability to understand existing approaches evaluate their suitability and modify or tune them for specific application needsrather than developing entirely new algorithms from scratch. They have a proven track record of translating these algorithms into efficient FPGA implementations building high-throughput low-latency data-processing pipelines on FPGAs; performing fixed point conversion and hardware optimization; validating numerical accuracy and output quality against golden algorithm models; and collaborating across hardware firmware and software teams to deliver mission-critical solutions to DoD Intelligence Community and Civil space customers.

Duties and Responsibilities

• Work within a multi-discipline team of engineers designing advanced processing imaging sensor RF networking and data storage solutions for space applications utilizing the latest FPGA technologies (with a strong emphasis on AMD (Xilinx) devices such as Zynq UltraScale MPSoC Zynq UltraScale RFSoC and Versal ACAP).
• Architect FPGA-based pipelines for image/video or other sensor data processing and compression including data acquisition pre-processing transformation compression and output formatting for space-based systems.
• Analyze existing image/video processing and compression algorithms (often developed in MATLAB or similar environments) understand their operation and performance characteristics and adapt or tune them for specific application performance and implementation constraints.
  Use MATLAB (and optionally Simulink or similar tools) to evaluate and refine existing algorithms establish golden reference models for output quality rate/distortion behavior and numerical accuracy and support their translation into hardware implementations.
• Translate MATLAB-level algorithms and specifications into FPGA architectures by:
  • Partitioning functionality between FPGA logic embedded processors and other accelerators.
  • Performing fixed-point analysis quantization and word-length optimization.
  • Mapping algorithms to DSP blocks memory structures and streaming data paths.
• Create and maintain complete FPGA designs using VHDL or Verilog and when applicable Vivado IP Integrator with emphasis on efficient data-path architecture deterministic latency and high-throughput implementations.
• Code simulate and verify a wide range of RTL modules for FPGAs including:
  • DSP-oriented processing blocks (filters transforms resampling and related operations).
  • Compression and decompression modules based on standard or custom approaches.
  • Control logic and interfaces to external peripherals and sensors or other data sources.
• Create and maintain comprehensive simulation testbenches (e.g. SystemVerilog) to:
  • Verify functional correctness of processing and compression modules.
  • Compare FPGA results against MATLAB golden models.
  • Achieve high code coverage and regression robustness.
• Develop and maintain IP-core-level and top-level design documentation interface control documents and performance/quality reports.
• Participate in and lead code reviews and design reviews.
• Collaborate closely with hardware and software engineers throughout integration to ensure processing and compression designs are correctly implemented configured and controlled at the system level including driver/software API definition where needed.
• Support system verification in an electronic lab environment including data capture evaluation of processing and compression performance and system-level debug using FPGA ILA-based tools (Vivado HW Debugger Chipscope SmartDebug).
• Provide technical leadership on imaging and compression architectures across multiple programs influencing technology roadmaps IP reuse strategies and standard algorithmic approaches within Trident SES.
• Mentor junior and mid-level engineers.
• Perform other duties as assigned.

Required Qualifications

• Bachelors degree in Computer Engineering Electrical Engineering or related technical degree
• Minimum of 6 years of related experience with a bachelors degree OR 4 years of experience with a masters degree
• Experience implementing signal processing algorithms (preferably related to image/video processing and/or data compression) in FPGA hardware including fixed-point conversion resource and throughput optimization and validation against algorithmic models.
• Ability to understand analyze and adapt existing algorithms for specific applications and constraints.
• Experience with RTL logic design and coding using VHDL or Verilog
• Experience with MATLAB or similar algorithmic modeling tools.
• Highly productive self-motivated person able to contribute as an individual and work within a distributed team

Preferred Qualifications

• Experience designing with Xilinx (AMD) FPGAs using Vivado or ISE
• Experience designing with Microsemi (Microchip) FPGAs using Libero
• Experience with logic simulation tools such as Modelsim/Questasim and/or Aldec
• Familiarity with lab test equipment such as logic analyzers oscilloscopes signal generators spectrum analyzers etc.
• Experience using revision control systems such as Git
• Linux
• C/C
  
  

Pay Information

Full-Time Salary Range: $97000 - $180000

Please Note: Actual compensation offered will be determined based on several factors including but not limited to relevant experience skills education certifications internal equity business considerations and geographic location where applicable.

Benefits

Hired applicants may be eligible for benefits including but not limited to:

• Health benefits
• Medical
• Dental
• Vision
• Basic life with AD&D
• Short term disability
• Long term disability
• Ancillary (Voluntary life with AD&D accident critical illness hospital and pet)
• Spending accounts (HSA FSA and DCFSA)
• Paid time off
• Holidays
• 401(k) (including company match)
• Tuition reimbursement
• Leaves (Parental maternity and military)
• Annual discretionary bonus (for eligible roles)

Trident Systems reserves the right to change or assign other duties to this position.

Trident Systems is an affirmative action and equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race color religion age sex national origin disability status genetics protected veteran status sexual orientation gender identity or expression or any other characteristic protected by federal state or local laws. To request reasonable accommodation to participate in the job application or interview process please contact.

Pay Transparency: The contractor will not discharge or in any other manner discriminate against employees or applicants because they have inquired about discussed or disclosed their own pay or the pay of another employee or applicant. However employees who have access to the compensation information of other employees or applicants as a part of their essential job functions cannot disclose the pay of other employees or applicants to individuals who do not otherwise have access to compensation information unless the disclosure is (a) in response to a formal complaint or charge (b) in furtherance of an investigation proceeding hearing or action including an investigation conducted by the employer or (c) consistent with the contractors legal duty to furnish information.