Senior Engineer, PLL Design

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To provide the best candidate experience amidst our high application volumes each candidate is limited to 10 applications across all open jobs within a 6-month period.

Advancing the Worlds Technology Together

Our technology solutions power the tools you use every day--including smartphones electric vehicles hyperscale data centers IoT devices and so much more. Here youll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of whats possible and powering the future.

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. Were dedicated to empowering people to be their true selves. Together were building a better tomorrow for our employees customers partners and communities.

Samsung Semiconductor Inc. (SSI) is advancing the worlds technology. As a leader in Memory System LSI and LCD technologies our US teams contribute to breakthroughs in 5G SOC memory and display. With our global perspective and diversity of thought we proudly serve our customers around the world. We are looking for team members who share our commitment to learning and growth and excel when collaborating within and across teams.

Samsung Semiconductor Inc is looking for a talented Senior/Staff PLL Designer with strong background and hands-on experience in PLL and clock generation circuit design. The candidate will work on the design and development of high-performance PLL and clocking subsystems for RF transceivers SerDes and high-speed I/O applications in advanced deep-submicron CMOS technologies.

What Youll Do

• Design PLLs and clock generation circuits (integer-N fractional-N digital PLLs clock multipliers/dividers) for RF and SerDes applications
• Design critical PLL building blocks including VCO/DCO charge pumps loop filters phase/frequency detectors dividers and phase interpolators
• Perform PLL system-level modeling noise analysis and jitter budgeting using Matlab/Simulink
• Drive design verification including transistor-level simulation Monte Carlo analysis and silicon correlation
• Collaborate with digital layout and systems teams to deliver PLL IPs meeting performance power and area targets
• Support bring-up characterization and debug of silicon prototypes in the lab

What You Bring

• Bachelors with 5 years of experience or Masters with 3 years of experiences or PhD with 0 years of experience in a related field.
• Extensive hands-on experience designing PLLs in deep sub-micron CMOS (5nm-28nm) including at least one of: integer-N fractional-N digital PLL or sub-sampling PLL topologies
• Deep understanding of PLL system theory: phase noise jitter loop dynamics reference spurs and fractional spurs
• Proficiency in IC design CAD tools such as Spectre SpectreRF and AMS simulator
• Strong Matlab/Simulink skills for behavioral modeling and system-level analysis
• Familiarity with Verilog/SystemVerilog for mixed-signal simulation
• Solid understanding of layout-sensitive design and ability to guide critical PLL layout (LC tank charge pump reference path)
• Lab characterization experience: phase noise measurement jitter analysis and spectrum analysis equipment
• Experience with RTL design (Verilog/SystemVerilog) to implement PLL-related digital calibration circuits including frequency calibration phase calibration and background self-calibration logic
• Excellent problem-solving analytical and communication skills

Base Pay Range

$138000 - $206000 USD