Enter a job title or keyword
Senior Digital Design Engineer
Job Location:
Job Location:
San Jose, CA - USA
Yearly Salary:
USD 130000 - 200000
Yearly Salary:
Posted:
7 September 2026 (5 hours ago)
Posted:
Application Deadline:
5 December 2026
Application Deadline:
Vacancies:
1 Vacancy
Vacancies:
Job Summary
Description
Team Credo is looking for a Senior PHY RTL Design Engineer to join our mission to transform this role you will be responsible for the RTL architecture design implementation and verification of advanced SerDes PHY Digital Signal Processing (DSP) blocks used in next-generation networking AI data center and high-performance computing products. The ideal candidate possesses strong digital design fundamentals hands-on RTL development experience and a good understanding of high-speed SerDes architecture. This position will be onsite at our San Jose CA HQ.
Base salary range is $130000 - $200000 a year. The base salary offer will depend on factors such as education experience training skills qualifications and location. This position is also eligible for a discretionary bonus equity and a full range of medical and other benefits.
Why Credo
Team Credo is looking for a Senior PHY RTL Design Engineer to join our mission to transform this role you will be responsible for the RTL architecture design implementation and verification of advanced SerDes PHY Digital Signal Processing (DSP) blocks used in next-generation networking AI data center and high-performance computing products. The ideal candidate possesses strong digital design fundamentals hands-on RTL development experience and a good understanding of high-speed SerDes architecture. This position will be onsite at our San Jose CA HQ.
Base salary range is $130000 - $200000 a year. The base salary offer will depend on factors such as education experience training skills qualifications and location. This position is also eligible for a discretionary bonus equity and a full range of medical and other benefits.
Why Credo
- Purpose: We invest in what matters. From meaningful-future shaping projects to competitive compensation we empower you to grow your career while making a lasting impact.
- People: Connection starts within. We collaborate celebrate wins and create an environment where everyone can do their best work.
- Possibilities: Our belief shapes whats next. Our technology powers the most reliable and energy-efficient connections around the world and our team powers new products and markets that come next.
Requirements
Basic Qualifications
Basic Qualifications
- BS/MS/PhD in Electrical Engineering Computer Engineering or related field.
- 5 years of digital design experience (or equivalent expertise for senior candidates).
- Strong RTL development skills using System Verilog.
- Experience designing high-speed communication or DSP hardware.
- Solid understanding of fixed-point arithmetic RTL implementation.
- Experience with ASIC development flow (e.g. Lint CDC/RDC Synthesis Timing analysis).
- Familiarity with EDA tools from Synopsys Cadence or Siemens.
- Strong debugging and problem-solving skills.
- Experience with high-speed SerDes standards such as PCIe Ethernet.
- Understanding of SerDes receiver and transmitter architectures and DSP algorithms (e.g. LMS adaptation timing recovery).
- Familiarity with Python or other scripting languages.
- Understanding of MATLAB or C/C modeling.
- Knowledge of mixed-signal PHY architecture and analog/digital interfaces.
- Experience of mixed-signal PHY simulations.
- Experience supporting silicon bring-up and post-silicon validation.
- Exposure to advanced process nodes (7nm 5nm 3nm or beyond).
Required Experience:
Senior IC
About Company
Credo delivers high-speed, energy-efficient connectivity solutions powering AI, cloud computing, and hyperscale networks up to 1.6T.
