Physical Design Engineer- Sunnyvale, CA

Hi

Job Title: Physical Design Engineer

Location- Sunnyvale CA- Onsite

Duration: Long Term contract

We have below longterm contract and onsite job opening.

If you are interested Please send your updated resume with below

YOUR CURRENT LOCATION:

VISA STATUS:

AVAILABILITY:

RELOCATE: YES / NO

EXPECTED RATE ALL INC ON RATE ON C2C/1099:

Key Responsibilities:

Need a PDE with front end experience who is good with Synthesis PDE flow and placement optimization.

We are hiring an experienced Physical Design Engineer to join a high-performing silicon engineering team supporting one of the worlds leading technology organizations in Sunnyvale CA. This is an exciting opportunity to work on cutting-edge ASIC/SoC designs and collaborate with talented engineers throughout the chip development lifecycle.

Key Responsibilities:

Drive RTL synthesis and optimization to achieve performance power and area (PPA) goals.

Perform floorplanning for complex ASIC/SoC designs while ensuring optimal timing congestion and power distribution.

Collaborate closely with RTL design engineers to provide actionable feedback that improves RTL quality synthesis results and overall implementation.

Analyze netlists and identify opportunities for optimization to improve design quality and implementation efficiency.

Work cross-functionally with architecture RTL verification and physical design teams to ensure smooth design convergence.

Support timing closure by identifying implementation bottlenecks and recommending design improvements.

Participate in design reviews and contribute to continuous process and methodology improvements.

Required Qualifications :

Bachelors or Masters degree in Electrical Engineering Computer Engineering or a related field.

Strong hands-on experience in ASIC/SoC physical design with 10 years of industry experience.

Expertise in RTL synthesis and timing optimization.

Solid experience with floorplanning for advanced technology nodes.

Strong understanding of netlist optimization and physical implementation methodologies.

Experience collaborating with RTL/design teams to improve design quality and implementation efficiency.

Excellent communication and cross-functional collaboration skills.

Preferred Skills :

Experience with industry-standard EDA tools for synthesis and physical design.

Strong understanding of timing congestion power and area optimization techniques.

Experience working on high-performance CPU GPU AI/ML or networking SoCs is a plus

Additional Information :

All your information will be kept confidential according to EEO guidelines.

Remote Work :

No

Employment Type :

Contract