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Physical Design Engineer
Job Location:
Job Location:
Austin, TX - USA
Monthly Salary:
Not provided by the employer
Monthly Salary:
Posted:
8 September 2026 (15 hours ago)
Posted:
Application Deadline:
6 December 2026
Application Deadline:
Vacancies:
1 Vacancy
Vacancies:
Job Summary
At Staffworxs we dont just connect talent we power transformation. Headquartered in Frisco TX with teams in Bengaluru and Hyderabad we combine global reach with deep expertise. Our Digital & Data Analytics practice drives growth and innovation for some of the worlds top brands who continue to retain us as their trusted partner. If youre ready to make an impact youre in the right place.
Job Details:
Role: Physical Design Engineer
Location: Austin TX or San Jose CA (Onsite)
Duration: Long term Contact
Responsibilities
Staffworxs is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive workplace for all employees regardless of race color religion gender sexual orientation national origin age disability or veteran status.
Job Details:
Role: Physical Design Engineer
Location: Austin TX or San Jose CA (Onsite)
Duration: Long term Contact
Responsibilities
- Own the full-chip physical design floorplan from architecture handoff through implementation including die sizing partition planning macro and memory placement and pin/port alignment across hierarchical block boundaries.
- Define and drive top-level chip integration strategy including partition abutment feedthrough planning channel allocation and implementation of repeating structures to ensure scalable and clean hierarchical integration.
- Lead top-level PPA (Power Performance Area) optimization across the chip hierarchy balancing timing congestion routability power efficiency and area utilization.
- Architect review and optimize the chip-level power delivery network (PDN) collaborating closely with EM/IR and sign-off teams to ensure robust power integrity and reliability targets are met.
- Develop maintain and own top-level timing constraints (SDC) timing budgets and interface requirements partitioning constraints effectively across subsystem and block-level owners.
- Drive cross-functional reviews for floorplan timing power and physical integration identifying and resolving implementation bottlenecks early in the design cycle.
- Collaborate closely with ASIC vendors IP providers RTL STA Packaging and block-level Physical Design teams to ensure seamless integration of IPs and successful tape-out execution.
- Cadence Innovus
- Synopsys Fusion
Staffworxs is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive workplace for all employees regardless of race color religion gender sexual orientation national origin age disability or veteran status.
Required Experience:
IC
