Module Design Engineer Architect

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We are seeking a highly skilled Camera Design Engineer Architect to lead the end-to-end electrical architecture definition and system integration of next-generation camera modules across Apples product portfolio. This role focuses on architecting the complete electrical signal chain from image sensor to SoC ISP defining power delivery networks high-speed interface topologies and control-plane architectures that enable industry-leading imaging performance. The ideal candidate will possess deep electrical engineering expertise with extensive knowledge in mixed-signal design high-speed serial interfaces and camera subsystem architecture. Strong technical proficiency is required in understanding CMOS image sensor readout architectures MIPI CSI-2 ACI or ALPDP interface design camera actuator (VCM OIS) driver topologies flash/strobe subsystems and low-noise power management for imaging applications (including LDO/DC-DC selection PSRR budgeting decoupling strategy and dynamic power state transitions). The architect must have thorough understanding of camera module electro-optical performance trade-offs EMI/EMC considerations and signal integrity constraints to define electrical solutions that meet aggressive image quality power and form-factor targets in consumer electronics applications including iPhone iPad Mac Vision and wearable core architecture definition this role demands hands-on involvement across the full product lifecycle including driving pre-silicon architecture studies with SoC ISP and PMIC teams defining board-level schematic and layout guidelines for camera subsystems and ensuring architectural intent is preserved from concept through mass production. The architect will lead cross-functional design reviews and technical trade studies by providing quantitative analysis of architecture options respond to bring-up and validation issues with deep debug of high-speed signaling and power integrity and drive systematic root cause analysis on architectural gaps discovered during EVT/DVT/PVT phases. This position serves as a critical technical bridge between image sensor suppliers SoC design teams module mechanical designers and system product design requiring expertise in both camera electrical architecture and practical implementation in high-volume high-reliability manufacturing environments.

Define end-to-end electrical architecture for camera subsystems including sensor-to-SoC signal chain MIPI CSI-2 ACI ALPDP lane budgeting clocking topology reset/control sequencing and multi-camera synchronization schemesnArchitect power delivery networks for image sensors actuators (VCM/OIS) and flash subsystems including rail partitioning PSRR budgeting transient response requirements and low-noise regulator selection to meet stringent image quality targetsnLead high-speed interface design and signal integrity analysis for MIPI ACI or ALPDP lanes including channel budgeting connector/flex selection EMI mitigation and pre/post-layout SI/PI simulation correlationnDefine schematic and PCB/flex layout guidelines for camera modules and system boards including reference designs layer stackup requirements impedance targets and DFM/DFT rules for global manufacturingnDrive cross-functional architecture reviews with SoC ISP PMIC RF mechanical and optics teams to align on power budgets thermal envelopes form factor constraints and testability requirementsnPartner with image sensor and actuator suppliers to influence next-generation silicon roadmaps review datasheets and errata and negotiate interface power and reliability specificationsnSupport EVT/DVT/PVT bring-up and validation by leading debug of high-speed link failures power integrity issues EMI/ESD events and image-quality-linked electrical root causesnLead FACA (Failure Analysis and Corrective Action) investigations by developing electrical characterization methodologies and diagnostic strategies to identify root causes of camera subsystem failures across engineering builds and mass productionnAnalyze electrical margin data temperature/voltage corner sweeps and yield signatures to drive design guardbands screening strategies and preventive design changes across product generationsnMaintain comprehensive architecture documentation including block diagrams interface specifications power state tables timing diagrams and compliance matrices for internal teams and suppliersnParticipate in design reviews with camera module system board and product design teams to ensure architectural integrity testability and validation coverage throughout the product lifecyclenInterface with camera algorithm ISP firmware and system software teams to translate imaging use cases (HDR ProRAW Cinematic mode low-light high-frame-rate video) into concrete electrical architecture and power state requirements

BS degree in Electrical Engineering Computer Engineering or a related fieldnExperience in electrical architecture mixed-signal design or camera/imaging subsystem development for consumer electronicsnExperience defining or designing camera subsystems including image sensor interfacing actuator drivers and low-noise power delivery on rigid PCB flex or SiP substratesnExperience with high-speed serial interface design (MIPI CSI-2 D-PHY C-PHY) including signal integrity analysis channel simulation and lab correlation

Masters or PhD in Electrical Engineering or relevant field and 10 years relevant industry experiencenAbility to lead EVT/DVT/PVT bring-up own FACA processes and resolve line-down or yield-impacting issues in fast-paced production environmentsnWorking knowledge of imaging and interface standards and specifications (MIPI CSI-2 ACI ALPDP I2C/I3C SPMI SPI MIPI CCS EMI/EMC standards IEC ESD)nExperience with camera factory testing equipment End2End imaging validation methods and electro-optical data interpretation for quality controlnExcellent communication and collaboration skills to work effectively with cross-functional teams including SoC design PMIC algorithms mechanical optics manufacturing quality and suppliersnExperience with statistical analysis tools and methodologies (SPC DOE 6-Sigma) applied to electrical characterization and yield engineering