Low Power Design Engineer

Would you like to join Apples growing wireless silicon development team Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient / low power design and new technologies that transform the user experience at the product level all of which is driven by a world-class vertically integrated engineering this highly visible role you will be at the center of low power logic design efforts with a critical impact on getting functional products to hundreds of millions of customers quickly. Will you join us and do the work of your life here

In this role you will be responsible for designing power management logic for complex wireless communication you join us and do the best work of your life here

Define SoC power management features to meet product power management with XF teams to verify power management Power team on power analysis and post-silicon correlation silicon bring up and debug support.

Minimum requirement of a bachelors track record in power / clock / reset management logic in Verilog management logic verification and debug ASIC low power design techniquesnKnowledge of CDC RDC STA and in scripting languages (Shell Perl or Python).nKnowledge and experience on common SOC components e.g. CPU fabric problem solving and analytical skills.

SoC level power management logic top level integration architecture -silicon functional debug and power correlation experience.