Lead Design Engineer

At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology.

We offer amazing opportunities to grow no matter where you are in your career.

At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadenceis a pivotal leader in electronic design building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software hardware and IP that turn design concepts into reality. Cadence customers are the worlds most innovative companies delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer hyperscale computing 5G communications automotive aerospace industrial and health.

The Cadence Advantage

• The opportunity to work on cutting-edge technology in an environment that encourages you to be creative innovative and to make an impact.
• Cadences employee-friendly policies focus on the physical and mental well-being of employees career development providing opportunities for learning and celebrating success in recognition of specific needs of the employees.
• The unique One Cadence One Team culture promotes collaboration within and across teams to ensure customer success
• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
• You get to work with a diverse team of passionate dedicated and talented individuals who go above and beyond for our customers our communities and each otherevery day.

Job Responsibility

Palladium and Protium are high-capacitive high-performance hardware assisted verification for complexed System-On-Chip (SOC). This role is to implement verify timing closure to tape out Palladium and Protium SOCs.

• Work on RTL synthesis and floorplanning
• Build clock trees and perform optimizations
• Close timing IR drop and physical verification
• Review and Document designs for taping out
• Interface with Front End RTL design teams and Back End Verification teams

Position Requirements/Qualifications:

• BSdegreeinElectricalEngineeringwithaminimumof5yearsofexperienceORMSwithaminimumof3yearsofexperience
• Experience with Cadence tools such as Innovus Tempus QRC Voltus and Pegasus
• Experience with advanced technologies like 5nm 3ns and 2nm nodes
• Experience using Linux servers Script development using Shell/Perl/TCL/Python
• Detailed knowledge about industry standard interfaces such as PCI Express DDR LPDDR SRAM UCIe etc.

Were doing work that matters. Help us solve what others cant.