Hardware Engineer, Physical Design

Normal Computing builds silicon that turns thermal noise from an obstacle into a computational resource. Conventional chips spend most of their energy forcing determinism onto physics; ours compute with it. Stochastic in-memory asynchronous: the result is 10-100 more AI inference per dollar per watt.

We co-design the full stack: AI-native EDA systems in production with the worlds largest semiconductor companies and the advanced ASICs they make possible. Backed by $85M from the worlds leading deep-tech investors and built by scientists engineers and operators from the labs that built modern computing.

Normal works as one team across New York Silicon Valley London Copenhagen and Seoul. We hire people who want the hardest version of their craft across every discipline at every seniority.

As a Physical Design Engineer at Normal you will own the end-to-end silicon realization path taking complex architectures from synthesis and physical floorplanning all the way through timing signoff and GDSII tapeout. Sitting at the intersection of custom ASIC design and our hardware-algorithm co-designed systems you will shape physical feasibility early in the design cycle by working shoulder-to-shoulder with RTL and architecture teams. Youll drive the full backend implementation flowoptimizing floorplanning place-and-route (P&R) clock tree synthesis (CTS) static timing analysis (STA) and physical verification (DRC/LVS) to achieve aggressive power performance and area (PPA) targets.

We are looking for a seasoned engineer who thrives in cross-functional environments and takes pride in tapeout-proven execution. The ideal candidate brings a meticulous approach to physical signoff maintains clarity in fast-paced build cycles and is excited to solve the physical constraints of novel computing architectures.

• Physical Implementation & Flow: Lead the full netlist-to-GDSII physical design flow including floorplanning power grid design placement clock tree synthesis (CTS) and place-and-route (P&R).

• Timing Closure & STA: Own static timing analysis (STA) timing constraints creation/validation and signoff timing closure across all operating corners and modes.

• Power Area and Signal Integrity: Drive physical optimization for power performance and area (PPA) as well as power integrity (IR/EM) and crosstalk analysis.

• Physical Signoff & Verification: Execute full chip/block physical signoff checks including DRC LVS ERC and antenna fixes ensuring seamless handoff to the foundry.

• Design & Floorplan Reviews: Collaborate closely with RTL architecture and DFT teams to influence early floorplanning macro placement pin assignments and physical feasibility.

• Tapeout & Post-Silicon Support: Create and execute tapeout checklists manage final stream-out processes and support post-silicon physical debugging and bring-up as needed.

• Tapeout Track Record: At least 3 successful tapeouts from netlist to signoff ideally across advanced technology nodes.

• PD Flow Expertise: Deep hands-on experience with industry-standard physical design tools (e.g. Innovus IC Compiler II Tempus PrimeTime Pegasus Calibre) across floorplanning P&R CTS and signoff timing closure.

• Backend Debugging Instincts: Strong problem-solving skills in analyzing and resolving STA timing bottlenecks IR/EM drop issues crosstalk and complex DRC/LVS signoff violations.

• Cross-Functional Feasibility: Ability to collaborate effectively with RTL architecture and DFT teams to influence floorplanning pin placement and early physical feasibility.

• Experience at an AI or high-performance compute (HPC) chip startup where design verification and PD work in tight iteration cycles.

• Experience with custom memory/macro floorplanning hierarchical top-level implementation or advanced packaging (e.g. chiplets 2.5D/3D integration).

• Hands-on experience developing or maintaining automated TCL/Python scripting frameworks for physical design flows.

Equal Employment Opportunity Statement

Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race color religion sex sexual orientation gender identity national origin disability veteran status or any other legally protected status.

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Required Experience:

IC