GPU Top Level Physical Design Engineer

Do you love creating elegant solutions to highly complex challenges Do you intrinsically see the importance in every detail As part of our Silicon Technologies group youll help design and manufacture our next-generation high-performance power-efficient GPU. You will ensure Apple products and services can seamlessly and expertly handle the tasks that make them beloved by millions. Joining this group means youll be crafting and building the technology that fuels Apples devices. Together we enable our customers to do all the things they love with their devices. This role requires a mix of strategic engineering along with hands-on technical work. You will be responsible for implementing complete chip design from netlist to tapeout. You will have hands on experience in physical design and large chip integration. nnJoin us!

As a GPU Top Level Physical Design engineer you will collaborate with FE team to understand RTL and drive physical aspects early in design cycle. You will drive innovation with the physical design team as you develop methodologies and best known methods that will enable best-in-class GPU design. You will develop PD guidelines and checklists drive execution and supervise progress. Be the focal point for place and route integration at the top level. You will need to communicate and drive the needs of PD with cross-functional teams that will enable achieving the goals of the back-end design for the project.

Minimum of BSc in EE and some relevant with ASIC integration including Floorplanning Clock and Power distribution global signal planning I/O planning and hard IP with hierarchical design approach top-down design budgeting timing and physical with Floorplanning tools Pu0026R flows global timing verification and Physical Design Verification Flows is required.

Experience integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical with Physical Design topics: multiple voltage and clock domains ESD solutions and mixed signal block with large subsystem designs (u003e20M gates) with frequencies in excess of 1GHz applying brand new with various process related design issues including Design for Yield and Manufacturability multi Vt strategies and thermal track record in solving complex PD and cross functional problems driving results directly and or directing a team of engineers to innovate and execute on world class of GPU architecture and design with Floorplanning tools Pu0026R flows global timing verification and Physical Design Verification Flows is required.