GPU Electrical Analysis Engineer

Do you love creating elegant solutions to highly complex challenges Do you intrinsically see the importance in every detail As part of our Silicon Technologies group youll help design and manufacture our next-generation high-performance power-efficient GPU. Youll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means youll be responsible for crafting and building the technology that fuels Apples devices. Together you and your team will enable our customers to do all the things they love with their devices. This exciting role requires a mix of strategic engineering along with hands-on technical work. Youll be responsible for realizing the complete electrical analysis closure from early design planning to tapeout. You will have hands on experience in physical design and large chip integration. nJoin us!

As a GPU Electrical Analysis engineer you will work closely with the Physical Design team to design power grid specification that achieves the best balance between power integrity targets and PNR performance power and Area (PPA). You will be involved with the definition of on-die power switch topology wake-up schemes and in-rush control. Collaboration with internal teams to drive bump map custom RDL routing and package design/optimization will be required. You will develop test structures procedures/automation and analysis methodologies for electrical analysis challenges. You will perform Power Integrity EM and ESD analysis drive feedback and recommend design solutions. Finally you will communicate and drive the needs of PD and Electrical Analysis with cross-functional teams that will enable achieving the goals of the back-end design for the project.

Experience planning implementing and analyzing power delivery designing and analyzing power delivery schemes with power with Signal/Power Integrity checks including Electromigration Static IR and Dynamic Voltage drop with global power integrity tool (e.g. Redhawk Voltus).nMinimum BS/MS in EE or similar fields and some years of experience

Experience with on-die high frequency power delivery and exposure to off-die concepts and with bump planning and redistribution layer routing strategies including methods for working with IO bumps and edge encroachment with ASIC integration including Floorplanning Clock and Power distribution global signal planning I/O planning and hard IP with large SoC designs (u003e20M gates) with frequencies in excess of 1GHz using innovative record in solving complex PD and cross functional problems driving results directly and or directing a team of engineers to innovate and execute on world class GPU design and simulation background a plus but not with global timing verification SPICE simulation/analysis and Physical Design Verification Flows.