FE Engineer
Sunnyvale, CA - USA
Job Summary
* Building a test bench creating test vectors and running the verification environment to verify that the subsystem you designed works properlyn* Synthesize the subsystem into logic and perform Static Timing Analysis (STA) on the design to make sure it meets the timing requirementsn* Designing integrating and verifying a system fabric bus into a subsystem
nDigital Logic Design knowledgenVerilog/System Verilog RTL language design entrynSynopsys/Cadence synthesisnSynopsys PrimeTime Static Timing Analysis (STA)nSynopsys (VCS)/Cadence(Incisive) simulation nStrong problem solving and analytical skillsnStrong communication skills combined with team-oriented approaches to own the verification efforts in a specific area of the design
* Experience/exposure writing specifications and documentationn* Experience/exposure with verifying logic design hardwaren* Experience/exposure to front-end tools and methodologies
Required Experience:
IC
About Company
Ask Siri to name the most successful company in the world and it might respond: Apple. And it's not just out of familial pride. Apple consistently ranks highly in profit, revenue, market capitalization, and consumer cachet. In 2018, the company became the first reach a trillion dollar ... View more