Distinguished Engineer, Front-End Silicon Architecture

What You Will Own

Connectivity Architecture

Own architecture for IO chiplet designs facilitating PCIe Gen 7 UCIe die-to-die

interconnect and protocol bridging to Ethernet fabrics (e.g. ESUN); define the functional

partitioning interface contracts and performance budgets that flow down to RTL

Select and implement SerDes-based protocols based on system requirements

evaluating link-training approaches equalization strategies error-containment and

PHY/MAC boundary trade-offs

Define and document coherency and interconnect fabric architecture using standard

(CHI AXI) or proprietary interfaces for each subsystem to optimize system performance

Produce clean unambiguous architecture specifications that serve as the single source

of reference for RTL verification and firmware teams

RTL Development & Logic Design Oversight

Translate architecture specifications into RTL implementation guidelines; work directly

with the RTL team to ensure high-quality implementation

Own the logic design review process: establish review criteria chair micro-architecture

review meetings and sign off on RTL that meets specification

Write production RTL when project timelines or technical complexity demand it

especially when architectural intent must be demonstrated through code

Identify and resolve RTL-level issuestiming closure risks clock-domain crossings

reset strategiesat the earliest possible stage

Specification & Cross-Functional Leadership

Write and maintain macro-architecture requirement documents micro-architecture

specifications and interface control documents (ICDs) that meet tape-out quality

standards

Serve as the technical liaison between architecture and RTL implementation teams

driving feasibility alignment and preserving architectural intent during implementation

Collaborate with verification leads to ensure architecture intent is captured in test plans

and that corner cases identified during verification feed back into specification updates

Represent architecture positions with executive leadership customers and standards

bodies where relevant

What We Are Looking For

Required Experience

20 years of experience in front-end silicon architecture and/or logic design on highvolume

production SoCs or ASICs

Deep expertise in high-speed serial interconnect protocols: PCIe (Gen 5/6/7) UCIe

CXL Ethernet at 100G; understanding of SerDes architecture link-layer state

machines and PHY/MAC interface design

Strong command of on-chip fabric architectures (CHI AXI4/AXI5 ACE) with hands-on

experience making key coherency fabric trade-offs at the block and subsystem level

Practical RTL development skills (SystemVerilog preferred); comfortable reviewing and

when necessary authoring RTL for complex control-plane

Strongly Preferred

Experience architecting an IO chiplet or die-to-die subsystem including UCIe adaptation

layer design re-timers and power performance trade-off analysis

Familiarity with emerging Ethernet-based fabric protocols for AI infrastructure (e.g. Ultra

Ethernet Consortium / ESUN) and their latency and congestion-management

implications

Tape-out ownership at leading-edge nodes (TSMC N3/N2 or equivalent): familiarity with

process-node constraints that influence architecture decisions

Experience with AI inference SoC architecture: systolic arrays HBM/LPDDR memory

subsystems or inference accelerator interconnect design

Leadership Qualities

Serve as the technical authority responsible for driving complex cross-functional issues

to closure throughout the product lifecycle from requirements to production

Able to lead by technical authorityteams adopt your architecture because your

proposals are rigorous clearly documented and account for implementation constraints

Precise structured written communicator: your specifications leave no room for

ambiguity and anticipate the questions RTL or verification teams will ask

Comfortable operating in a fast-moving startup: you scope proposals to what is buildable

in the available time and know when good enough is the right architecture call

Collaborative and direct: you raise technical concerns early and constructively hold the

line on quality without creating friction and remain approachable to junior team

members

Role Details

Reports To: Executive Engineering Leader with regular direct engagement with the CEO (&

CTO) on product and customer strategy

Location: San Francisco Bay Area (preferred); hybrid considered for exceptional candidates