Digital Layout Design Engineer

Do you have a passion for crafting entirely new solutionsnnAs part of our Digital Design Engineering group youll take imaginative and revolutionary ideas and determine how to turn them into reality! You and your team will apply engineering fundamentals and start from scratch if needed bringing forward-thinking ideas to the real world. Join us and youll help design the tools that allow us to bring customers experiences theyve never before will be part of an exciting silicon design group that is responsible for designing state-of-the-art ASICs. We have an extraordinary opportunity for Digital Layout Designers!nnIn this highly visible role you will be a member of Apples custom layout team working on the latest technology nodes to create extraordinary custom digital macros libraries etc. This is a fast paced work environment with endless learning opportunities working in the design team with members of integration CAD circuit and technology engineering.

Imagine yourself at the center of our SOC design effort collaborating with all fields playing a strategic role of getting functional products to millions of customers quickly. n nYou will have the opportunity to integrate and come-up with new ideas as well as work with a team of hardworking engineers. As a member of the layout team of the microprocessor group you will be responsible to deliver PDV clean layout including the following: n n-tDesigning complex custom layout for digital circuits in deep SubMicron CMOS technologies. n n-tReviewing and analyzing floorplans and complex circuits with circuit designers. n n-tRunning a complete set of layout design verification tools available on megacells completed. n n-tWorking with the circuit design team to plan schedule work and negotiate layout tradeoffs as needed. n n-tInterpretation of LVS DRC and ERC report to find the fastest way to complete layouts. n n-tExceed engineering specifications and expectations. n n-tUse advanced CAD tools mask design knowledge to layout corrections and robust physical design representation of circuits.

Bachelors degree in relevant field of study plus 3 years of relevant experience

We are looking for applicants experience in custom layout design of deep SubMicron CMOS level proficiency in layout floorplanning standard cell planning and hierarchical layout understanding of issues with RC delay electromigration self heating and cross failure prone layout structures dedicatedly work with designers for the best approach to communication skills and able to work with multi-functional skills on interpretation of CALIBRE DRC ERC LVS etc. of MENTOR GRAPHICS or CADENCE layout toolsnScripting skills in CSH PERL or SKILL are considered a plus but not in layout automation is considered a plus but not in memory compiler development is considered a plus but not designing low noise low power datapaths or Memory layout structures etc.