Digital Circuit Design Engineer

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APPLE INC has the following available in Austin Texas. Ensure that all pre-silicon deliveries of custom IPs for Apple Socs are bug free. This involves working closely with circuit and RTL (Register Transfer Level) designers to validate design functionality optimize performance and ensure that the design complies with the architectural specifications. Review design and architectural specifications to understand use cases and corner conditions then translate these into testbenches including key verification components such as stimulus generation checkers assertions and functional coverage utilizing SystemVerilog and UVM (Universal Verification Methodology) which offers a more standardized and scalable verification approach. Ensure that the RTL/Verilog design files are bug free and match the specifications and requirements. Run and debug simulation regressions triage failures track bugs and perform detailed coverage analysis to ensure high-quality verification results. Generate and analyze Toggle Coverage reports to verify complete signal toggling for each design. Leverage industry-standard tools such as Verdi and Cadence lndago for debugging simulation-waveforms analyzing environment hierarchies and bug resolution in complex verification environments. Develop and use Perl and Python-based automation scripts for automatic testbench generation and verification workflows improving efficiency and reducing manual effort. Work with circuits pertaining to SRAMs register files and caches applying academic knowledge in VLSI and circuit design to verify custom memory architectures. Refactor testbench code to enhance reusability and maintainability eliminating hardcoded values and ensuring a modular verification environment. Use version control systems such as Perforce documentation platforms like Confluence and proprietary task management tools for effective cross-functional collaboration. 40 hours/week.

Bachelors degree or foreign equivalent in Computer Engineering Electrical Engineering or a related and/or education must include:nnUtilizing SystemVerilog or Verilog to develop RTL verification testbenches for digital circuit designs including simulation and analysis of design Universal Verification Methodology (UVM) or equivalent methodology to develop verification environments including monitors and RTL design verification and debug using industry-standard waveform and simulation debug tools to identify functional failures and isolate root digital memory and custom circuits (e.g. SRAM register files or other IP blocks) including read/write operations timing behavior and corner-case formal verification tools including Logical Equivalence Checking (LEC) or ESPCV or equivalent to validate equivalence between RTL and synthesized Python Perl or C to automate verification flows regression execution and test regression management and revision control systems to execute automated regression test suites and track changes across RTL and verification digital circuit fundamentals including synchronous logic finite state machines timing analysis and clock/reset behavior to support design verification.

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