Datacenter Compute SoC Performance Modeling Engineer

Category: Algorithm & Architecture Primary Location: San Jose California Additional Locations: San Diego California; Portland Oregon; Austin Texas Experience Level: 5 years of relevant industry experience

About the Team

The companys Data Center team is at the forefront of innovation developing cutting-edge technologies that power the worlds most advanced data centers.

Our team brings together system architects advanced packaging technology developers and SoC design experts dedicated to creating high-performance power-efficient scalable and reliable solutions for data center applications.

We collaborate closely across technical disciplines to push the boundaries of compute technology and shape the future of cloud computing hyperscale infrastructure and AI data centers.

Role Summary

The company is seeking a highly skilled Datacenter Compute SoC Performance Modeling Engineer to help define and optimize our next-generation cloud and data center processors.

In this role you will develop and maintain high-speed cycle-accurate and transaction-level architectural simulators used to evaluate design trade-offs identify performance bottlenecks and project system performance across a broad range of data center workloads.

You will work closely with CPU and compute-core architects SoC architects IP architects workload characterization teams and RTL designers to ensure that our silicon delivers industry-leading performance per watt and scales efficiently for modern hyperscale infrastructure.

Key Responsibilities

Performance Simulator Development

Design develop and maintain cycle-accurate and transaction-level performance models using C and SystemC.

Model key components of multi-core data center SoCs including:

o CPU and compute cores

o Cache and memory subsystems

o Network-on-Chip interconnects

o High-speed I/O interfaces

o PCIe and CXL subsystems

Improve simulator speed scalability accuracy and maintainability.

Workload Analysis and Profiling

Analyze and characterize modern data center workloads including:

o Cloud-native applications

o Microservices

o Databases

o Big data analytics

o Virtualized workloads

o AI and machine-learning data-processing pipelines

Translate workload behavior into architectural requirements and performance targets.

Architectural Performance Exploration

Conduct what-if analyses and large-scale architectural design sweeps.

Evaluate trade-offs involving:

o Core counts

o Cache sizes and configurations

o Memory capacity and bandwidth

o Memory and interconnect latency

o NoC topology

o High-speed I/O performance

o Multi-die system configurations

Recommend architectural configurations that optimize performance power efficiency and scalability.

Performance Bottleneck Identification

Identify microarchitectural and system-level performance bottlenecks.

Analyze limitations related to compute throughput cache behavior memory bandwidth latency coherency traffic and interconnect congestion.

Propose innovative hardware and software solutions to address identified bottlenecks.

RTL and Silicon Correlation

Collaborate with RTL verification emulation and post-silicon validation teams.

Correlate performance models against:

o RTL simulations

o Hardware emulators

o FPGA prototypes

o Post-silicon measurements

Refine model behavior and assumptions to maintain a high level of accuracy.

Performance Tooling and Infrastructure

Develop and enhance performance analysis tools and infrastructure.

Build:

o Trace collection and analysis tools

o Data visualization dashboards

o Automated performance regression pipelines

o Reporting and comparison frameworks

Use Python and related data-analysis libraries to automate performance analysis and improve engineering productivity.

Cross-Functional Collaboration

Partner with CPU SoC memory interconnect I/O software and firmware teams.

Present complex performance results and architectural trade-offs to technical teams and leadership.

Contribute to architectural specifications design reviews and technology roadmap decisions.

Qualifications

Education

Bachelors or Masters degree in one of the following fields:

Computer Engineering

Electrical Engineering

Computer Science

A related technical discipline

Professional Experience

5 years of relevant industry experience in:

o CPU performance modeling

o Compute-core performance modeling

o SoC performance modeling

o System-level performance modeling

o Computer architecture analysis

Data Center Workload Experience

Experience profiling or analyzing hyperscale and data center workloads such as:

SPEC CPU

Cloud microservices

Databases

Big data analytics

Virtualized environments

Server and cloud infrastructure workloads

AI and machine-learning data-processing workloads

Required Technical Expertise

Programming and Software Development

Expert-level proficiency in modern C preferably C14 C17 or later.

Strong understanding of object-oriented software design.

Experience developing large-scale modular and maintainable simulation software.

Strong scripting skills in Python or Perl for automation data analysis and performance reporting.

CPU and Compute Architecture

Deep understanding of high-performance CPU microarchitecture including:

o Out-of-order execution

o Branch prediction

o Instruction scheduling

o Pipeline behavior

o Speculative execution

o Memory-level parallelism

Alternatively strong understanding of advanced computation engines such as:

o Processing-element arrays

o Graph-based compute architectures

o Domain-specific accelerators

o Parallel compute engines

Memory and Cache Architecture

Comprehensive knowledge of:

o Memory hierarchies

o Cache architectures

o Cache coherency protocols

o Memory bandwidth and latency behavior

Familiarity with coherency protocols such as:

o MESI

o MOESI

Experience with main memory technologies including:

o DDR

o LPDDR5 and LPDDR6

o HBM

Interconnects and High-Speed I/O

Familiarity with on-chip interconnect protocols and architectures including:

o AMBA CHI

o AXI

o Network-on-Chip architectures

Understanding of high-speed I/O protocols including:

o PCIe

o CXL

Knowledge of multi-die and chiplet architectures including:

o UCIe

o Die-to-die interconnects

Performance Modeling Frameworks

Hands-on experience with one or more of the following:

gem5

Sniper

SystemC-based modeling environments

Trace-driven simulators

Execution-driven simulators

Proprietary performance simulation frameworks

Building architectural simulators from the ground up

Communication Skills

Ability to clearly communicate complex performance data and architectural trade-offs.

Strong written and verbal presentation skills.

Ability to work effectively with cross-functional engineering teams and senior technical leadership.

Work Locations

This position is open in the following locations:

San Jose California

San Diego California

Portland Oregon

Austin Texas

Compensation

The base salary range for this position is:

$211000$356000 per year

Employees may also be eligible for:

Performance-based bonuses

Short-term incentive programs

Long-term incentive programs

Actual total compensation will depend on the individuals skills relevant experience qualifications and work location.

Benefits

The company provides a comprehensive benefits package that may include:

Comprehensive health insurance coverage

Life insurance

Disability insurance

Retirement savings plan

401(k)

Company-paid holidays

Paid sick leave

Paid vacation

Parental leave

Additional employee benefits and incentive programs

Equal Employment Opportunity

The company is an Equal Opportunity Employer committed to inclusion and diversity.

Employment decisions are made without regard to age ancestry color physical or mental disability family or medical leave status gender gender expression gender identity genetic information marital status medical condition military or