Datacenter Compute SoC Architect

My clients Data Center team is at the forefront of innovation developing cutting-edge technologies that power the worlds most advanced data centers.

Our team brings together system architects advanced packaging technology developers and SoC design experts to create high-performance power-efficient scalable and reliable solutions for data center applications.

We work collaboratively across disciplines to push the boundaries of compute technology and shape the future of cloud computing and AI infrastructure.

We are seeking a highly experienced and visionary Datacenter Compute SoC Architect to lead the definition design and optimization of companys next-generation high-performance computing SoCs.

In this critical role you will define the system-on-chip architecture for scalable data center processors balancing power performance and area requirements while supporting demanding cloud-scale and AI workloads.

You will collaborate closely with CPU and compute core architects IP designers performance modeling teams packaging engineers and software and firmware teams to deliver world-class silicon solutions.

Key Responsibilities

SoC Architecture Definition

Lead the architectural definition of next-generation data center compute SoCs.

Define core and instance counts cache hierarchies coherent interconnects and memory subsystems.

Establish architectural requirements that support scalable cloud computing and AI workloads.

IP Selection and Integration

Define technical requirements and drive architectural decisions for internal and third-party IP.

Evaluate and integrate technologies including:

o PCIe Gen 5 and Gen 6

o CXL

o DDR5 and HBM memory controllers

o Network-on-Chip architectures

o Security enclaves and related security IP

Power Performance and Area Optimization

Conduct detailed power performance and area trade-off analysis.

Optimize the SoC architecture to meet aggressive data center efficiency scalability and performance-per-watt targets.

Evaluate architectural alternatives and identify the optimal balance between performance cost power consumption and silicon area.

Advanced Packaging Strategy

Collaborate with packaging technology teams on multi-die and chiplet-based architectures.

Define requirements for die-to-die interconnect protocols including UCIe.

Support the development of advanced thermal and packaging solutions for high-performance compute platforms.

Hardware and Software Co-Design

Partner with firmware operating system and cloud infrastructure software teams.

Ensure the hardware architecture effectively supports:

o Modern hypervisors

o Virtualization technologies

o Cloud-native workloads

o Data center operating environments

o AI and high-performance computing applications

Performance Modeling

Work closely with performance modeling teams to define workloads use cases and architectural evaluation criteria.

Guide the development of C and SystemC architectural models.

Analyze simulation results to identify performance bottlenecks and architectural optimization opportunities.

Technical Leadership

Develop detailed SoC architecture specifications and technical documentation.

Serve as the technical lead throughout:

o RTL implementation

o Design verification

o System validation

o Silicon bring-up

Provide architectural guidance and resolve complex cross-functional technical issues.

Qualifications

Education

Bachelors or Masters degree in:

o Electrical Engineering

o Computer Engineering

o Computer Science

o Or a related technical discipline

Professional Experience

10 years of industry experience in one or more of the following areas:

o SoC architecture

o CPU or compute architecture

o System architecture

At least 3 years of experience focused on:

o High-performance server SoCs

o Data center processors

o Network processor SoCs

o Other high-performance infrastructure compute platforms

Technical Expertise

The ideal candidate should have expertise in the following areas:

CPU and Compute Architecture

Deep understanding of high-performance CPU or compute architectures including:

o ARM

o x86

o RISC-V

Coherent Fabrics and Interconnects

Extensive knowledge of coherent fabrics and on-chip interconnect technologies including:

o ARM AMBA CHI

o AXI

o Proprietary Network-on-Chip architectures

o Cache-coherent interconnect protocols

Memory and Cache Architecture

Strong expertise in:

o Memory hierarchy design

o Cache architectures

o Cache coherency protocols

o Memory bandwidth and latency optimization

Experience with main memory technologies including:

o DDR4

o DDR5

o LPDDR

o HBM

High-Speed I/O

Solid understanding of high-speed interfaces and data center connectivity technologies including:

o PCIe

o CXL

o Ethernet

Communication and Collaboration

Exceptional written and verbal communication skills.

Ability to translate complex architectural concepts into clear and actionable specifications.

Proven ability to influence and collaborate with cross-functional engineering teams.

Work Locations

This position is open in the following locations:

San Jose California

San Diego California

Portland Oregon

Austin Texas

Compensation

The base salary range for this position is:

$211000$356000 per year

Employees may also be eligible for:

Performance-based bonuses

Short-term incentive programs

Long-term incentive programs

Actual total compensation will depend on the individuals skills qualifications and relevant professional experience.

Benefits

The company provides a comprehensive benefits package which may include:

Health insurance coverage

Life insurance

Disability insurance

401(k) retirement savings plan

Company-paid holidays

Paid sick leave

Paid vacation

Parental leave

Additional employee benefits and incentive programs

Equal Employment Opportunity

The company is an Equal Opportunity Employer committed to inclusion and diversity.

Employment decisions are made without regard to age ancestry color physical or mental disability family or medical leave status gender gender expression gender identity genetic information marital status medical condition military or veteran status national