Datacenter Compute Accelerator Architect

Category: Algorithm & Architecture Primary Location: San Jose California Additional Locations: San Diego California; Portland Oregon; Austin Texas Experience Level: 8 years of relevant industry experience

About the Team

The companys Data Center team is at the forefront of innovation developing cutting-edge technologies that power the worlds most advanced data centers.

Our team brings together system architects advanced packaging technology developers and SoC design experts dedicated to creating high-performance power-efficient scalable and reliable solutions for data center applications.

We collaborate closely across technical disciplines to push the boundaries of compute technology and shape the future of cloud computing hyperscale infrastructure and AI data centers.

Role Summary

The company is seeking a highly specialized Datacenter Compute Accelerator Architect to lead the architecture design and integration of dedicated hardware accelerators within our next-generation data center silicon.

As data center workloads increasingly rely on heterogeneous computing offloading critical functionsincluding cryptography data compression networking memory movement and AI processingfrom the main CPU or compute cores is essential to maximizing system-level performance and efficiency.

In this role you will define the architecture of on-chip uncore accelerators and ensure their seamless integration with coherent interconnects memory hierarchies virtualization infrastructure and the hypervisor software stack.

You will work at the intersection of hardware and software to deliver scalable high-throughput low-latency acceleration solutions for hyperscale cloud environments.

Key Responsibilities

Accelerator Architecture Definition

Define the architecture and microarchitecture of tightly coupled uncore accelerators.

Develop detailed architecture specifications for acceleration engines such as:

o Cryptography and security engines

o Compression and decompression engines

o Direct Memory Access engines

o Tensor and AI compute engines

o Data analytics offload engines

o High-speed packet-processing accelerators

o Memory-movement and data-processing engines

Define accelerator performance targets interfaces data paths programming models and resource requirements.

SoC Integration

Integrate accelerator blocks into coherent SoC interconnects and memory subsystems.

Work with technologies such as:

o AMBA CHI

o AMBA AXI

o Proprietary Network-on-Chip architectures

Define efficient data flows between accelerators CPU cores caches system memory and I/O devices.

Optimize latency and bandwidth utilization while preventing accelerator traffic from negatively affecting CPU or compute-core performance.

Address coherency ordering quality-of-service and backpressure requirements.

Hardware and Software Co-Design

Partner closely with kernel firmware driver compiler and systems software engineers.

Define:

o Software programming models

o Device APIs

o Command and descriptor formats

o Queue structures

o Memory-management mechanisms

o Interrupt and completion models

Ensure accelerator capabilities are accessible scalable and efficient across modern operating systems and cloud software environments.

Virtualization and Security

Design accelerator architectures that support secure multi-tenant cloud environments.

Implement or define support for hardware virtualization technologies including:

o SR-IOV

o Scalable IOV

o PASID

o IOMMU

o SMMU

Ensure secure and isolated execution across virtual machines containers and cloud tenants.

Address memory protection address translation access control fault isolation and secure data movement.

Power Performance and Area Analysis

Conduct detailed power performance and area trade-off analyses.

Evaluate the value of dedicated hardware acceleration compared with CPU-based or software-based execution.

Collaborate with performance modeling teams to simulate:

o Accelerator throughput

o End-to-end latency

o Memory bandwidth requirements

o Interconnect utilization

o Power efficiency

o Scalability under heavy data center workloads

Recommend architectural configurations that optimize performance per watt and silicon area.

Performance Modeling and Workload Analysis

Use architectural simulators and performance-analysis tools to evaluate accelerator designs.

Analyze representative data center workloads and identify functions suitable for hardware offload.

Assess emerging workloads in areas such as:

o AI and machine-learning inference

o Database query processing

o Storage processing

o NVMe over Fabrics

o Networking and packet processing

o Security and encryption

o Data compression

Translate workload requirements into accelerator architecture and performance targets.

Technical Execution and Leadership

Serve as the primary technical focal point throughout:

o Architecture definition

o RTL design

o Design verification

o Performance validation

o Emulation

o Silicon bring-up

Review RTL implementation to ensure alignment with architectural specifications.

Resolve complex cross-functional issues involving architecture firmware software verification and physical design.

Ensure the final silicon implementation meets its intended functional performance power and scalability goals.

Basic Qualifications

Education

Bachelors or Masters degree in one of the following fields:

Computer Engineering

Electrical Engineering

Computer Science

A related technical discipline

Professional Experience

8 years of industry experience in one or more of the following:

o CPU or compute architecture

o SoC architecture

o Hardware accelerator architecture

o System architecture

Relevant experience should include a focus on:

o Data center silicon

o Server processors

o Storage silicon

o Networking silicon

o High-performance compute platforms

Required Technical Expertise

Hardware Acceleration

Deep understanding of hardware acceleration algorithms and architectures for one or more of the following areas:

Cryptography including:

o AES

o SHA

o RSA

Tensor and AI compute

Compression and decompression including:

o zstd

o gzip

High-speed packet processing

DMA and data-movement engines

Data analytics acceleration

Storage-processing acceleration

Interconnect and Memory Architecture

Strong knowledge of on-chip coherent fabrics and interconnects including:

o AMBA AXI

o AMBA CHI

o Proprietary Network-on-Chip architectures

Strong understanding of:

o Memory hierarchies

o Cache architectures

o Cache coherency protocols

o Memory ordering

o Bandwidth and latency optimization

o Quality-of-service mechanisms

Virtualization and Memory Management

Solid understanding of hardware virtualization technologies.

Experience or familiarity with:

o IOMMU

o SMMU

o SR-IOV

o Scalable IOV

o PASID

o PCIe virtualization

o Address translation and isolation

Understanding of accelerator sharing and isolation in virtualized and multi-tenant environments.

Programming and Modeling

Proficiency in C or C for:

o Architectural modeling

o Performance modeling

o Functional prototyping

Proficiency in Python for:

o Data analysis

o Automation

o Performance reporting

o Simulation-result processing

Emerging Data Center Workloads

Familiarity with hardware offload opportunities involving:

AI and machine-learning inference

Database queries and analytics

Storage processing

NVMe over Fabrics

Network packet processing

Memory movement

Security and compression workloads

Pre-Silicon Modeling Tools

Experience using architectural simulators and performance-analysis tools.

Familiarity with gem5 is strongly preferred.

Experience evaluating whether a workload should be executed through:

o Dedicated hardware acceleration

o General-purpose CPU execution

o Software-based processing

Ability to quantify accelerator benefits in performance power latency throughput and area.

Communication and Collaboration

Strong written and verbal communication skills.

Ability to translate complex architectural concepts into clear technical specifications.

Ability to present performance trade-offs and architecture recommendations to cross-functional engineering teams and technical leadership.

Work Locations

This position is open in the following locations:

San Jose California

San Diego California

Portland Oregon

Austin Texas

Compensation

The base salary range for this position is:

$211000$356000 per year

Employees may also be eligible for:

Performance-based bonuses

Short-term incentive programs

Long-term incentive programs

Actual total compensation will depend on the individuals skills relevant experience qualifications and work location.

Benefits

The company provides a comprehensive benefits package that may include:

Comprehensive health insurance coverage

Life insurance

Disability insurance

Retirement savings plan

401(k)

Company-paid holidays

Paid sick leave

Paid vacation

Parental leave

Additional employee benefits and incentive programs

Equal Employment Opportunity

The company is an Equal Opportunity Employer committed to inclusion and diversity.

Employment decisions are made without regard to age ancestry color physical or mental disability family or medical leave status gender gender expression gender identity genetic information marital status medical condition military or veteran status national origin political affiliation race religious creed