CAD Engineer – Design Verification Methodology
Beaverton, OR - USA
Job Summary
As a member of our CAD team you will develop maintain and enhance existing sophisticated software systems for regression-testing Apples silicon designs in software simulation to find and report defects in our chip designs and thus ensure that Apple tapes-out world-class silicon. Your experience and innovative ideas will inform the design of the next generation of these regression systems. Your experience and insight your skill at diagnosing the root cause of complex problems and your ability to guide engineers who come to you with problems will be important contributions to an extended CAD team that comprehensively supports Apples DV and chip design engineering efforts. You will work closely with EDA vendors to incorporate new capabilities of their commercial tools and to resolve problems.
Minimum of BS degree 10 years of relevant experiencenExperience developing maintaining and enhancing an existing system for regressing RTLnExperience debugging vendor tool problemsnPython programming background is required
Experience with TCL or Perl is a plusnExperience with artificial intelligence and machine learning nExperience with interacting with DV team(s) to help solve their in implementing new functionality to solve emerging problems or to optimize already existing in Verilog and SystemVerilog; familiarity with VHDL a with VCS XCelium or Modelsim simulation with Cadence or Synopsys Emulation communications skills are required and prior customer support experience is a with Verdi and/or Indago is considered a of C and C is a plus.
Required Experience:
IC
About Company
Ask Siri to name the most successful company in the world and it might respond: Apple. And it's not just out of familial pride. Apple consistently ranks highly in profit, revenue, market capitalization, and consumer cachet. In 2018, the company became the first reach a trillion dollar ... View more