ASIC Physical Design Engineer

ASIC Physical Design Engineer

At Tektronix we believe innovation starts with our customer. This approach has led us to a seventy-five-year history of delivering outstanding solutions to customers in virtually every industry. Our inclusive engineering culture is hardworking inquisitive and always eager to learn and grow. We are customer obsessed in our daily work and continuously strive for improvement to conceptualize the best solutions possible. We are an ever-evolving team that is always looking for opportunities to develop people and resolve tough problems together.

We are seeking an experienced ASIC Physical Design Engineer to join one of Tektronixs design centers in Louisville CO or Beaverton this role you will work on all aspects of physical design and implementation of SOC devices targeted at our next-generation products. You will collaborate closely with an exceptional cross-functional team to deliver industry-leading solutions using world-class design tools.

Responsibilities

Execute ASIC digital physical design implementation from RTL or gate-level netlist through GDSII including floor-planning placement clock tree synthesis routing and design closure.

Drive place-and-route execution using industry-standard EDA tools optimizing designs for timing power area signal integrity and routability.

Perform static timing analysis and timing verification across multiple modes and corners resolving setup hold clocking and constraint-related issues to achieve timing closure.

Support physical signoff activities including DRC LVS formal equivalence checking extraction IR drop electromigration and signal integrity analysis.

Collaborate with RTL design verification DFT analog packaging and product architecture teams to resolve implementation issues and ensure a timing-closed manufacturable tapeout-ready design.

Develop and maintain scripts flows documentation and review materials that improve physical design methodology automation quality and schedule predictability.

Minimum Qualifications

BS in Electrical Engineering or equivalent experience.

5 years of hands-on experience ASIC physical design from RTL to verified GDS.

Hands-on experience with ASIC or SoC physical design implementation including floorplanning power planning place-and-route clock tree synthesis routing and design closure.

Working knowledge of RTL-to-GDSII physical design flows and the ability to resolve implementation issues related to congestion timing power area and signal integrity.

Experience with static timing analysis timing constraints multi-mode multi-corner timing verification and timing closure at the block or SoC level.

Familiarity with physical signoff checks and related debug activities including DRC LVS extraction formal equivalence checking IR drop electromigration and crosstalk analysis.

Proficiency with industry-standard physical design and timing tools from vendors such as Cadence Synopsys or Siemens EDA.

Strong scripting and automation skills using Tcl Python Perl or shell scripting to support physical design flows debug reporting and methodology improvement.

Provide feedback to RTL and packaging design teams to improve design hand-off quality and standard work processes.

Basic knowledge of industry standard ECO practices.

Preferred Qualifications

10 years of hands-on experience ASIC physical design from RTL to verified GDS.

MS or PhD in Electrical Engineering or equivalent experience.

Principal-level experience leading physical design implementation for complex ASIC or SoC programs including floorplanning power planning place-and-route clock tree synthesis routing ECOs and full-chip or major subsystem closure.

Proven ability to define and drive RTL-to-GDSII physical design strategy resolve complex congestion timing power area signal integrity and manufacturability tradeoffs and deliver tapeout-quality results on schedule.

Advanced expertise in static timing analysis timing constraints multi-mode multi-corner timing verification clocking methodology ECO implementation and timing closure at the SoC subsystem and critical-block levels.

Deep experience driving physical signoff readiness and debug including DRC LVS extraction formal equivalence checking IR drop electromigration crosstalk antenna reliability and tapeout-quality verification closure.

Expert proficiency with industry-standard physical design timing extraction and signoff tools from vendors such as Cadence Synopsys or Siemens EDA including the ability to define flows debug tool issues and guide methodology decisions.

Demonstrated technical leadership managing internal execution and external ASIC design service providers including defining scopes of work reviewing deliverables tracking milestones resolving technical issues and ensuring quality schedule and tapeout readiness.