ASIC Engineer, Annapurna Labs

Amazon Web Services provides a highly reliable scalable low-cost infrastructure platform in the cloud that powers hundreds of thousands of businesses in 190 countries around the world. We have data center locations in the U.S. Europe Singapore and Japan and customers across all industries.

Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team youll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia our custom designed machine learning inference datacenter server. Our success depends on our world-class server infrastructure; were handling massive scale and rapid integration of emergent technologies. Were looking for an ASIC Design Engineer to help us trail-blaze new technologies and architectures while ensuring high design quality and making the right trade-offs.

Key job responsibilities
- Develop and implement high-performance area and power-efficient RTL designs to meet project specifications and targets
- Conduct in-depth analysis of designs microarchitectures and architectures to optimize trade-offs between features power consumption performance and area requirements
- Create microarchitectures implement SystemVerilog RTL and deliver synthesis and timing-clean designs with appropriate constraints
- Execute lint and clock domain crossing quality checks to ensure design integrity
- Collaborate closely with cross-functional teams including architects fellow designers verification specialists pre- and post-silicon validation teams and synthesis timing and back-end experts

The ideal candidate will have a strong background in ASIC design proficiency in SystemVerilog and excellent analytical and problem-solving skills. Experience with high-performance and power-efficient designs is highly desirable.

You will thrive in this role if you:
- Have a Learn and Be Curious mindset
- Have familiarity with key components such as interconnects DMAs Memory sub-systems accelerator engines debug and system level architectures
- Have a strong drive to innovate explore new solutions and contribute to the companys intellectual property through patents

- Bachelors degree in Electrical Engineering or a related field
- Experience identifying bugs in architecture algorithms functionality and performance with strong overall debugging skills
- Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing

- Masters degree or Ph.D. degree in Electrical Engineering or related field
- Experience with formal verification techniques including abstraction and end-to-end checking
- Experience with current and upcoming RF standards in cellular (4G/5G) WiMAX 802.11ad microwave backhaul DVB-S2 / DVB-C or related broadband wireless standards
- Experience with industry standard tools and scripting languages (Python or Perl) for automation
- Experience with ARM and various DSP ISAs

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