ASIC Design Engineers — Design-for-Test (DFT) & Physical Design (Synthesis and Timing) – (Experienced, Lead, or Senior)

ASIC Design Engineers Design-for-Test (DFT) & Physical Design (Synthesis and Timing) (Experienced Lead or Senior)

Company:

The Boeing Company

Boeing Defense Space and Security is hiring ASIC Design Engineers Design-for-Test (DFT) & Physical Design (Synthesis and Timing) at various levels of experience to join the team in Mountain View CA.

Boeing Space Intelligence & Weapons Systems organization is seeking multiple ASIC engineers across experience levels to advance missioncritical digital subsystems. Candidates may focus on DesignforTest (DFT) / ASIC backend test infrastructure or on Physical Design (synthesis and static timing analysis) responsibilities. You will work on leadingedge ASICs used in space and aerospace systemsdriving architecture verification tapeout readiness silicon debug and crossdiscipline integration with architecture RTL verification DFT and external backend partners.

Position Responsibilities:

• Design and implement DFT architectures and test access mechanisms: TAP/JTAG IJTAG (IEEE 1687) Boundary Scan (BSCAN) MBIST memory BIST and scan compression.
• Develop and validate TAP/JTAG and IJTAG infrastructures; produce BSDL/ICL/PDL artifacts; support ATPG pattern generation and coverage optimization.
• Drive pattern generation memory test validation atspeed test silicon debug (scan atspeed bringup) and postsilicon validation.
• Perform synthesis equivalence checking static timing analysis (STA) constraints generation/management timing convergence and ECO implementation at block and chip level.
• Support clean netlist handoffs and predictable convergence by partnering with RTL verification DFT backend partners and vendors.
• Support chiplevel integration toplevel timing closure signoff readiness and tapeout activities.
• Contribute to methodology development automation tool evaluations flow documentation and deployment of best practices for nextgeneration products.
• Troubleshoot complex crossdomain timing and CDC issues; propose and implement robust repeatable fixes.
• Coordinate with external partners/customers on custom DFT interfaces security and backend flows as applicable.
• Mentor engineers and lead technical efforts (for senior/lead levels).
• Occasional travel and afterhours meetings during critical milestones.

How to make your application stand out: Please include a cover letter or brief summary of relevant DFT or ASIC physical design experience and specific examples of impact (e.g. achieved timing closure on Xnm blocks implemented MBIST with Y% coverage reduced ATPG time by Z% led ECOs to tapeout).

This position is expected to be 100% onsite. The selected candidate will be required to work onsite at the listed location.

Basic Qualifications (Required Skills/Experience):

• This position requires the ability to obtain a US Security Clearance for which the US Government requires US Citizenship as a condition of employment. An interim and/or final U.S. Secret Clearance Post-Start is required.
• Bachelor of Science degree in Engineering (with a focus in Electrical Mechanical or Aeronautical) Computer Science Data Science Mathematics Physics Chemistry or non-US equivalent qualifications directly related to the work statement
• 5 years of ASIC/FPGA design for test or physical design experience
• Proficiency in scripting for automation and analysis (Tcl Python Perl).

Preferred Qualifications (Desired Skills/Experience):

• Lead Level 4: 9 years related engineering experience and demonstrated technical leadership.
• Senior Level 5: 14 years related engineering experience and demonstrated technical leadership.
• Strong analytical problemsolving and communication skills
• Bachelors or Masters Degree in EE Computer Engineering/Science or related field.
• For DFT roles: Handson expertise with TAP/JTAG IJTAG (IEEE 1687) Boundary Scan (IEEE 1149.1) MBIST scan compression ATPG atspeed test and silicon debug. Familiarity with BSDL/ICL/PDL artifacts.
• For Physical Design roles: Practical experience in synthesis and static timing analysis (STA) constraints generation/management logic synthesis equivalence checking and ECO flows.
• Active U.S. Secret Clearance.
• Experience with large timingchallenging ASIC blocks crossdomain timing convergence and full physical design flow (synthesis floorplanning place & route CTS STA physical verification).
• Background in radiationhardened or spacequalified ASIC design.
• FPGA implementation experience including constraints and timing closure.
• Understanding of timing fundamentals and CDC concepts.
• Familiarity with UPF/CPF power intent power closure flows and DFT interplay with power domains.
• Requirements development and traceability experience.
• Experience working with external backend partners multidisciplinary teams and vendors.
• Familiarity with industrystandard EDA tools and DFT/physical design methodologies.
• Mentoring team leadership or formal technical lead experience.

Conflict of Interest:

Successful candidate for this job must satisfy the Companys Conflict of Interest (COI) assessment process.

Typical Education/Experience

Experienced Level 3: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering engineering technology (includes manufacturing engineering technology) computer science engineering data science mathematics physics or chemistry (e.g. Bachelor) and typically 5 or more years related work experience or an equivalent combination of technical education and experience or non-US equivalent the USA ABET accreditation is the preferred although not required accreditation standard.

Lead Level 4: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering engineering technology (includes manufacturing engineering technology) computer science engineering data science mathematics physics or chemistry (e.g. Bachelor) and typically 9 or more years related work experience or an equivalent combination of technical education and experience or non-US equivalent the USA ABET accreditation is the preferred although not required accreditation standard.

Senior Level 5: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering engineering technology (includes manufacturing engineering technology) computer science engineering data science mathematics physics or chemistry (e.g. Bachelor) and typically 14 or more years related work experience or an equivalent combination of technical education and experience or non-US equivalent the USA ABET accreditation is the preferred although not required accreditation standard.

Relocation:

This position offers relocation based on candidate eligibility. Note: Basic relocation will be offered for eligible internal candidates.

Drug Free Workplace:

Boeingis a Drug Free Workplace where post offer applicants and employees are subject to testing for marijuana cocaine opioids amphetamines PCP and alcohol when criteria is met as outlined in our policies.

Shift Work:

This position is for 1st shift.

Total Rewards:

At Boeing we strive to deliver a Total Rewards package that will attract engage and retain the top talent. Elements of the Total Rewards package include competitive base pay and variable compensation opportunities.

The Boeing Company also provides eligible employees with an opportunity to enroll in a variety of benefit programs generally including health insurance flexible spending accounts health savings accounts retirement savings plans life and disability insurance programs and a number of programs that provide for both paid and unpaid time away from work.

The specific programs and options available to any given employee may vary depending on eligibility factors such as geographic location date of hire and the applicability of collective bargaining agreements.

Pay is based upon candidate experience and qualifications as well as market and business considerations.

Summary pay range for Experienced (Level 3): $119850 - $162150

Summary pay range for Lead (Level 4): $146200 - $197800

Summary pay range for Senior (Level 5): $176800 - $239200

Language Requirements:

Not Applicable

Education:

Bachelors Degree or Equivalent

Relocation:

This position offers relocation based on candidate eligibility.

Export Control Requirement:

This position must meet U.S. export control compliance requirements. To meet U.S. export control compliance requirements a U.S. Person as defined by 22 C.F.R. 120.62 is required. U.S. Person includes U.S. Citizen U.S. National lawful permanent resident refugee or asylee.

Safety Sensitive:

This is not a Safety Sensitive Position.

Security Clearance:

This position requires the ability to obtain a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim and/or final U.S. Secret Clearance Post-Start is required.

Visa Sponsorship:

Employer will not sponsor applicants for employment visa status.

Contingent Upon Award Program

This position is not contingent upon program award

Shift:

Shift 1 (United States of America)

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