ASIC Design Engineer — Pixel IP

Do you love creating elegant solutions to highly complex challenges As part of our Hardware Technologies group youll help design our next-generation high-performance power-efficient system-on-chips (SoCs). You will ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions! Joining this group means youll be responsible for crafting and building the technology that fuels Apples devices. Together we will enable our customers to do all the things they love with their devices!nnIn this highly visible role you will be at the center of the Pixel IP design effort to capture and display beautiful images and video. You will collaborate with all disciplines making a critical impact getting functional products to millions of customers quickly.

As an ASIC Design Engineer in the Pixel IP design team you will work closely with architecture design and verification teams to design high performance and low power pixel processing engines. Apply your knowledge of computer architecture and digital design to create digital signal processing pipelines for capturing improving compressing decompressing and displaying digital still images and this front-end design role your tasks will include: ntDesign digital hardware by writing high-quality RTL or using a high-level synthesis methodology with embedded assertions and cover detailed micro-architectural with cross-functional teams to explore solutions that maximize performance while minimizing power and your design and optimize for power timing and closely with design verification and formal verification teams to debug and verify functionality and independently and manage deliverables to align with the project goals and support cross-functional engineering efforts.

Bachelors Degree in EE/CE and 10 years of relevant industry experience.

Extensive experience in SoC front-end ASIC RTL digital logic design using Verilog and System deep experience in media video pixel or display in low-power design techniques such as clock- and experience working cross-functionally with architecture design and verification teams to specify design and debug collaboration skills with excellent written and verbal communication with common on-chip bus protocols such as AMBA (AXI AHB APB).nExperience in front-end implementation tasks such as synthesis timing area/power analysis linting CDC/RDC and logic equivalence exposure to and knowledge of ASIC design methodology including familiarity with relevant scripting languages (Python Perl TCL).