ASIC Design Engineer Pixel IP DMA

Do you love creating sophisticated solutions to highly complex challenges As part of our Hardware Technologies group youll help design our next-generation high-performance power-efficient system-on-chips (SoCs). You will ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions! Joining this group means youll be responsible for crafting and building the technology that fuels Apples devices. Together we will enable our customers to do all the things they love with their devices!nnIn this highly visible role you will be at the center of the Pixel IP design effort in pixel processing. You will collaborate with all teams making a critical impact getting functional products to millions of customers quickly.

As a Pixel IP DMA Design Engineer in the Pixel IP team you will work closely with architecture design and verification teams to build high performance and low power DMA engines that coordinate moving large amounts of data between the memory system and the Pixel IP Engine. nnIn this front-end design role your tasks will include: n- Exploring solutions to enhance performance while minimizing power and areann- Detailing specifications and building RTL designsnn- Working with design verification and formal verification teams to verify functionality and performance

Bachelors Degree 10 years of experience

Experience in multimedia IP/SoC front-end ASIC RTL designnTight-knit collaboration skills with excellent written and verbal communication skillsnExperience working multi-functionally with architecture design and verification teams to specify design and debug designsnPrevious experience designing dedication DMA engines (especially related to machine learning applications) data storage memory controllers networking image processing and/or interconnectsnGood understanding of arbitration address translation caching on-chip interconnects and performance analysisnFamiliarity with common on-chip bus protocols such as AMBA (AXI AHB APB)nExperience in front-end implementation tasks such as synthesis area and power analysis linting and logic equivalence checks