ASIC Design Engineer — IP Integration & Implementation

Do you love creating elegant solutions to highly complex challenges As part of our Hardware Technologies group youll help design our next-generation high-performance power-efficient system-on-chips (SoCs). You will ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions! Joining this group means youll be responsible for crafting and building the technology that fuels Apples devices. Together we will enable our customers to do all the things they love with their devices!nnIn this highly visible role you will be at the center of the Pixel IP design effort to capture and display beautiful images and video. You will collaborate with all disciplines making a critical impact getting functional products to millions of customers quickly.

As an ASIC Design Engineer in the Pixel IP design team you be responsible for complex subsystem integration and implementation. You will work closely with architecture design and verification teams to build high performance and low power pixel processing engines. You will have responsibilities spanning all aspects of multimedia IP this front-end design role your tasks will include: ntWriting detailed micro-architectural and integration digital hardware design by writing high-quality RTL with embedded assertions and cover with physical design teams to optimize timing area and power for our designs in that our designs follow industry best practices for handling power clock and reset closely with design verification and formal verification teams to debug and verify functionality and independently and manage deliverables to align with the project goals and support cross-functional engineering efforts.

Bachelors degree and 10 years of relevant industry experience

Deep experience in IP/SoC design integration at the chip or subsystem level and exposure to and knowledge of ASIC/FPGA design methodology especially logic synthesis static timing analysis logic equivalence checking and working with physical design teams for floorplanning and timing with system design methodologies that contain multiple clock and reset with common on-chip bus protocols such as AMBA (AXI AHB APB).nExperience in low-power design issues tools and methodologies including UPF power intent specification highly exposure to and knowledge of ASIC design methodology including familiarity with relevant scripting languages (Python Perl TCL).nExperience in datapath and pixel-centric designs a collaboration skills with excellent written and verbal communication.