ASIC Design and Integration Engineer – Silicon Security
Cupertino, CA - USA
Job Summary
As an ASIC Design Engineer on the Silicon Security team you will be responsible for the micro-architecture RTL design and integration of secure subsystems. Your responsibilities will include:ntArchitecting and designing state-of-the-art security features working closely with Platform Architecture Design Verification to deliver high performance area and power efficient RTL Blocks on timentIntegrating security IPs into secure subsystem and ensuring timing performance and security requirements are integration issues across multiple IP blocks and coordinating with IP owners on interface and functionality concernsntDriving front-end quality flows from RTL to netlist including hands-on work with Lint CDC/RDC analysis UPF development timing and AI-assisted tools to enhance design quality and productivity.
Bachelors in Electrical Engineering Computer Engineering or a relevant field and 10 years of industry experience n10 years of RTL design experience using Verilog or SystemVerilog.
Experience with CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) analysis and with low-power design techniques and UPF (Unified Power Format).nSolid understanding of digital design fundamentals including synthesis timing closure and design for in cryptography and cryptographic algorithm with hardware security concepts including key management physical attack and with clock and reset architecture at the subsystem levelnStrong knowledge of AMBA bus protocols (AXI AHB APB). nExperience with hardware security concepts including key management physical attack and countermeasures
Required Experience:
IC
About Company
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