ASIC Design and Integration Engineer
Job Location:
Job Location:
Beaverton, OR - USA
Monthly Salary:
Not Disclosed
Monthly Salary:
Posted on:
Yesterday
Posted on:
Vacancies:
1 Vacancy
Vacancies:
Job Summary
Apples Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer to join our dynamic this role you will develop custom SoCs that drive the performance and efficiency of Apples products. You will work on cutting-edge technologies and collaborate with cross-functional teams to deliver groundbreaking solutions.
Design and Development: Design implementation and verification of complex ASICs. Develop RTL using SystemVerilog and perform : Engage with simulation-based and formal verification teams to ensure robust design and Testing: Collaborate with hardware and software teams to integrate digital designs into complex and Power Analysis: Conduct timing analysis and power optimization to achieve PPA and Reporting: Create detailed micro-architecture and design documentation.
Minimum of BS 10 years relevant industry experience
Experience: 8 years of proven experience in ASIC design including RTL design and verification. Hands-on experience with ASIC design tools and methodologies is Skills: Proficiency in SystemVerilog RTL design synthesis and timing -Solving: Strong analytical and problem-solving : Excellent communication and teamwork skills work effectively in cross-functional to Detail: Meticulous attention to detail and a commitment to delivering high-quality with high-speed I/O design and protocols. Knowledge of PCIe is a with custom ASIC design and FPGA on experience in all aspects of front-end chip development process (e.g. CDC/RDC LINT LEC etc.).nKnowledge of low-power design techniques and power optimization strategies.
Design and Development: Design implementation and verification of complex ASICs. Develop RTL using SystemVerilog and perform : Engage with simulation-based and formal verification teams to ensure robust design and Testing: Collaborate with hardware and software teams to integrate digital designs into complex and Power Analysis: Conduct timing analysis and power optimization to achieve PPA and Reporting: Create detailed micro-architecture and design documentation.
Minimum of BS 10 years relevant industry experience
Experience: 8 years of proven experience in ASIC design including RTL design and verification. Hands-on experience with ASIC design tools and methodologies is Skills: Proficiency in SystemVerilog RTL design synthesis and timing -Solving: Strong analytical and problem-solving : Excellent communication and teamwork skills work effectively in cross-functional to Detail: Meticulous attention to detail and a commitment to delivering high-quality with high-speed I/O design and protocols. Knowledge of PCIe is a with custom ASIC design and FPGA on experience in all aspects of front-end chip development process (e.g. CDC/RDC LINT LEC etc.).nKnowledge of low-power design techniques and power optimization strategies.
Required Experience:
IC
About Company
Ask Siri to name the most successful company in the world and it might respond: Apple. And it's not just out of familial pride. Apple consistently ranks highly in profit, revenue, market capitalization, and consumer cachet. In 2018, the company became the first reach a trillion dollar ... View more
