Graduate Verification Engineer

Cambridge UK Full-time Permanent Hybrid

Salary: 37000 - 40000

About us

Riverlanesmission is to master quantum error correction (QEC) and unlock a new age of human progress. From advances in material and climate science to complex chemistry simulation for new drug design quantum computers will help humanity solve some of its most important challenges. But without QEC the industrys defining technical challenge such breakthroughs can never be is the world leader in QEC technology. QEC is a complex problem that requires a range of skillstalentand passion.

Having raised more than $125M in funding to date to accelerate ourcutting-edgeR&D in quantum error correction (QEC) Riverlane partners with many of the worlds leading quantum hardware providers and government agencies to make fault-tolerant quantum computing a reality.Weremaking remarkable progress and growing fast.

About the role

We have an exceptional opportunity for a Graduate Verification Engineer to join our talented team of hardware designers and embedded software engineers. Together youll deliver fully verified high-performance and trusted systems.

In this exciting role youll have end-to-end visibility across the entire stack owning different aspects of verification and shaping how quality and reliability are built into our cutting-edge technology. You do not need a background in quantum computing! You will learn this along the way.

What you will do -specific responsibilities:

As aGraduate Verification Engineer at Riverlane you will:

• Help with developing and executing verification plans for hardware blocks in Quantum Error Correction Systems
• Learn and support the creation of testbenches using SystemVerilog and UVM
• Run simulations and perform debugging to resolve issues in collaboration with the design team
• Collaborate with multi-disciplinary teams to understand specifications and define verification strategies for Quantum Error Correction systems
• Learn and apply best practices in verification to make methodology improvements

What we need - Essential Skills/Experience:

• Bachelors or Masters degree in Electrical Engineering Computer Science or related discipline
• Understanding of Digital Logic Design
• Some familiarity with HDL languages (e.g. Verilog SystemVerilog) and simulation tools
• Good communication and problem-solving skills

Even better if you have

• Relevant academic projects/internships/work experience
• Exposure to scripting languages such as Python
• Understanding of Object-Oriented Programming
• Exposure to UVM

What can you expect from us

• A comprehensive benefits package that includesan annual bonus planprivate medical insurance life insurance and acontributory pension scheme

• Equity so that our team can share in the long-term success of Riverlane

• 28 days annual leaveplus bank holidays and enhanced family leave

• A diverse work environment that brings together experts in many fields (including software and hardware development quantum information theoryphysicsand maths) and over 20 different nationalities

• A learning environment that encourages individual team and company growth anddevelopment including a regular programme of learning events and training and conference budgets

How to apply

Please upload a CV and covering letter by clicking Apply. Your covering letter should explain why you are applying for the job and what skills and experience you can bring to the role.

We review CVs as we receive them and interview as soon as we have applications thatlooklike a good match. We do not use closing dates. So pleaseapply as soon as possible to avoidmissing out onthis role.

If you have any queries please contactcom.

Everyone is welcome at Riverlane. We are an equal opportunities employer and encourage applications from eligible and suitably qualified candidates regardless of age disability ethnicity gender gender reassignment religion or belief sexual orientation marital or civil partnership status or pregnancy and maternity/paternity.

Women and other underrepresented groups may be less likely to apply for a role unless they meet all ornearly allof the this applies to you we still encourage you to apply - you may be a great fit even if youdontmeet every single to hear from you.

If you need any adjustments made to the application or selection process so you can do your best please let us know. We will be happy to help.

GDPR notice: Riverlane collects and processes personal data in accordance with applicable data protection laws. If you are a European Job Applicant see theprivacy noticefor further details.