Senior Staff Engineer, Design Verification (Power & Analog ICs)

We are seeking a Senior Staff Design Verification Engineer to lead verification of the digital content embedded within power analog and mixed-signal IC products. This is a senior individual-contributor role requiring ownership of verification architecture methodology execution and sign-off at block and full-chip level. 

The successful candidate will build scalable verification environments from specifications develop verification plans and coverage strategies and verify control protection diagnostics communication trimming test and safety-related digital functions that interact closely with analog circuitry. 

You will be expected to work autonomously resolve ambiguous specification issues establish verification flows from scratch where required mentor engineers and provide clear evidence that the design meets functional and product requirements before tape-out. 

Responsibilities  

Verification Strategy & Ownership 

• Own block-level and full-chip digital verification strategy for power analog and mixed-signal IC products. 
• Develop verification plans from product and design specifications including feature extraction test intent coverage goals assumptions and sign-off criteria. 
• Decompose complex functions into reusable verification components and scalable environments. 
• Identify specification gaps and drive closure with architecture analog design digital design applications and test teams. 

Environment Development & Execution 

• Design and develop SystemVerilog/UVM-based testbenches agents scoreboards reference models assertions sequences and coverage models. 
• Set up verification flows from scratch where needed and own regression execution triage debug and closure. 
• Apply simulation assertion-based verification formal verification and FPGA or emulation techniques where they provide practical value. 
• Verify digital behavior across reset clock power-state fault trim communication test-mode and analog-interaction scenarios. 

Mixed-Signal DFT & Post-layout Support 

• Collaborate with analog and digital teams to define appropriate models and verify analog-digital interactions at the required abstraction level. 
• Support DFT verification scan and ATPG-related checks production-test vector development and test-mode verification. 
• Support gate-level simulation timing-aware verification and post-layout verification where required. 
• Contribute to silicon bring-up device evaluation root-cause analysis and documented workarounds for device errata. 

Technical Leadership & Methodology 

• Drive reusable verification methodology automation metrics documentation and review standards across projects. 
• Mentor and train verification engineers through reviews debug support and technical guidance. 
• Provide concise status coverage risk and sign-off assessments to project and technical leadership. 
• Influence architecture and design choices by identifying verification complexity observability gaps and product risks early. 

Qualifications :

• Bachelor or Masters degree in Electrical Engineering Electronics Engineering Computer Engineering or a related discipline. 
• 10 years of experience in digital verification including substantial hands-on experience with SystemVerilog and UVM. 
• Proven ownership of block-level and full-chip verification environments and sign-off for complex semiconductor products. 
• Strong knowledge of functional verification assertion-based verification formal verification regression frameworks coverage closure and debug methodologies. 
• Experience verifying digital logic embedded in PMICs power-management automotive audio or other mixed-signal integrated circuits. 
• Good understanding of RTL microarchitecture clocks resets low-power states register interfaces and common serial interfaces such as SPI I2C or UART. 
• Working knowledge of synthesis STA DFT scan insertion ATPG and gate-level verification to collaborate effectively across the development flow. 
• Experience with scripting or automation using Python TCL Perl shell or similar languages. 
• Proven ability to mentor engineers establish verification methodology and lead technical reviews without requiring formal people-management authority. 
• Self-driven results-oriented and able to deliver under tight schedules in a multisite and multicultural environment. 

Additional Information :

Renesas is an embedded semiconductor solution provider driven by its Purpose To Make Our Lives Easier. With a global team of over 21000 engineers and problem solvers in more than 30 countries we offer the opportunity to work on worldleading technology for Automotive Industrial Infrastructure and IoT shaping a safer healthier greener and smarter future.

At Renesas TAGIE is our culture grounded in being Transparent Agile Global Innovative and Entrepreneurial. It shapes how we work grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us

Renesas Electronics is an equal opportunity and affirmative action employer committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex race religion national origin gender gender identity gender expression age sexual orientation military status veteran status or any other basis protected by law. For more information please read our Diversity & Inclusion Statement.

Remote Work :

No

Employment Type :

Full-time