Senior Principal Engineer- Digital Design
Job Summary
Job Summary:
We are seeking an experienced Senior Principal Engineer - Digital Design to lead the micro-architecture design and execution of next-generation UA Link Switch solutions within the Memory Interface Division (MID). The ideal candidate will bring deep expertise in high-speed digital system design and SoC development with a proven track record delivering complex silicon products from architecture through production.
This role requires strong technical leadership in defining and implementing scalable switching and interconnect architectures that enable high-bandwidth low-latency connectivity for AI HPC and memory-centric systems.
Key Responsibilities:
- Lead digital architecture and design activities for UA Link Switch products.
- Define and drive microarchitecture RTL design integration and performance optimization of high-speed switching fabrics and interconnect subsystems.
- Collaborate with architecture verification firmware physical design signal integrity and system teams to ensure successful product execution.
- Drive end-to-end development from requirements definition through silicon bring-up and product qualification.
- Provide technical leadership across multiple engineering teams and mentor senior engineers.
- Analyze performance power area and scalability trade-offs to meet aggressive product goals.
- Participate in architectural reviews design audits and technical roadmap planning.
- Work closely with ecosystem and standards teams to align product implementation with evolving industry standards.
Qualifications :
- Bachelors Masters or Ph.D. in Electrical Engineering Computer Engineering or related discipline.
- 15 years of experience in digital ASIC/SoC development.
- Strong experience in one or more of the following areas:
- High-speed digital design
- SoC architecture and integration
- Switching fabric design
- Network-on-Chip (NoC)
- High-speed interconnects
- Memory subsystem design
- Microcontroller-based systems
- High-bandwidth data movement architectures
- Deep understanding of RTL design using Verilog/SystemVerilog.
- Experience with modern ASIC development flows including synthesis STA low-power methodologies and silicon bring-up.
- Strong debugging and performance analysis skills.
- Demonstrated ability to lead complex technical programs and influence cross-functional teams.
Preferred Qualifications:
- Prior experience in: High-speed SerDes-based systems Switching fabrics and packet processing architectures Memory interface technologies AI/HPC interconnect solutions PCIe CXL Ethernet UCIe or related high-speed protocols.
- Experience developing large-scale SoCs for networking compute storage or memory applications.
- Understanding of system-level architecture and board-level considerations for high-speed designs.
- Experience leading geographically distributed engineering teams.
- Strong communication and stakeholder management skills.
Additional Information :
Renesas is an embedded semiconductor solution provider driven by its Purpose To Make Our Lives Easier. With a global team of over 21000 engineers and problem solvers in more than 30 countries we offer the opportunity to work on worldleading technology for Automotive Industrial Infrastructure and IoT shaping a safer healthier greener and smarter future.
At Renesas TAGIE is our culture grounded in being Transparent Agile Global Innovative and Entrepreneurial. It shapes how we work grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.
We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.
Are you ready to join our team and shape the future with us
Renesas Electronics is an equal opportunity and affirmative action employer committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex race religion national origin gender gender identity gender expression age sexual orientation military status veteran status or any other basis protected by law. For more information please read our Diversity & Inclusion Statement.
Remote Work :
No
Employment Type :
Full-time
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