Principal Engineer-Physical Design

Job Summary:

We are seeking an experienced Senior Principal Engineer / Senior Manager Physical Design Lead to lead the implementation and delivery of next-generation high-performance SoC products built on advanced process technologies. This role will be responsible for driving the complete physical design execution of large-scale SoCs from floorplanning through tape-out while achieving aggressive performance power area and schedule targets. 

The ideal candidate will have a proven track record delivering complex 3nm and/or 5nm SoCs with deep expertise in physical implementation of extremely high-speed designs incorporating large digital subsystems high-speed SerDes interfaces mixed-signal blocks and advanced power management architectures. 

Key Responsibilities:

• Lead the end-to-end physical design execution of large and complex SoCs from floorplanning through GDS signoff. 
• Own implementation strategy execution planning risk management and tape-out readiness. 
• Drive floorplanning power planning placement clock tree synthesis routing timing closure signal integrity IR/EM closure and physical verification. 
• Collaborate closely with architecture RTL verification DFT package analog and product engineering teams to optimize implementation quality and schedule. 
• Define chip-level implementation methodologies and best practices to achieve challenging frequency power and area goals. 
• Lead timing closure for complex multi-clock high-frequency designs. 
• Partner with package and system teams to optimize overall product performance and signal integrity. 
• Drive implementation of advanced low-power architectures and ensure successful power-performance-area (PPA) optimization. 
• Lead physical design reviews signoff reviews and tape-out milestones. 
• Mentor senior physical design engineers and establish implementation excellence across the organization. 

Qualifications :

• Bachelors Masters or Ph.D. in Electrical Engineering Computer Engineering or related discipline. 
• 15-20 years of experience in ASIC/SoC physical design. 
• Proven experience leading physical design teams for large-scale high-performance SoCs. 
• Demonstrated success delivering advanced-node products preferably at 3nm and/or 5nm technology nodes. 
• Extensive experience across:  Floor planning and Partitioning Power Planning Placement and Optimization Clock Tree Synthesis (CTS) Routing and Congestion Analysis Timing Closure Signal Integrity Analysis IR Drop and Electromigration (EM) Closure Physical Verification and Signoff.
• Deep understanding of advanced-node implementation challenges including variation management power integrity and manufacturability. 
• Strong knowledge of industry-standard physical design and signoff flows. 
• Proven ability to lead large cross-functional teams and manage complex execution schedules.

Preferred Qualifications

• Experience implementing:  

1. High-performance SoCs operating at aggressive frequency targets 
2. Large-scale switching and interconnect architectures 
3. Network-on-Chip (NoC) based designs 
4. High-bandwidth data movement fabrics 
5. Multi-billion transistor designs 
6. Experience integrating and closing timing on:  
7. High-speed SerDes subsystems 
8. Mixed-signal and analog IPs 
9. Advanced PHY technologies 
10. Memory controller and high-speed interface designs 

• Strong understanding of package-level and system-level impacts on physical implementation and timing closure. 
• Experience with advanced packaging and multi-die/chiplet architectures. 
• Exposure to AI HPC networking data-center connectivity or memory infrastructure products. 
• Prior experience with high-performance switch fabrics Ethernet switching UALink or similar interconnect technologies is desirable. 
• Advanced Low-Power Expertise (Must Have) 
• The successful candidate must have hands-on experience architecting and implementing advanced power optimization techniques in advanced-node SoCs including: 
• Multi-voltage and multi-power domain designs 
• Dynamic Voltage and Frequency Scaling (DVFS) 
• Power gating and retention strategies 
• Clock gating methodologies 
• Adaptive power management techniques 
• UPF/CPF-based low-power implementation flows 
• Leakage optimization and dynamic power reduction 
• Low-power verification and signoff methodologies 
• Power-aware physical design and implementation closure. 

Additional Information :

Renesas is an embedded semiconductor solution provider driven by its Purpose To Make Our Lives Easier. With a global team of over 21000 engineers and problem solvers in more than 30 countries we offer the opportunity to work on worldleading technology for Automotive Industrial Infrastructure and IoT shaping a safer healthier greener and smarter future.

At Renesas TAGIE is our culture grounded in being Transparent Agile Global Innovative and Entrepreneurial. It shapes how we work grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us

Renesas Electronics is an equal opportunity and affirmative action employer committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex race religion national origin gender gender identity gender expression age sexual orientation military status veteran status or any other basis protected by law. For more information please read our Diversity & Inclusion Statement.

Remote Work :

No

Employment Type :

Full-time