Logic Lead

Be visionary

Teledyne Technologies Incorporated provides enabling technologies for industrial growth markets that require advanced technology and high reliability. These markets include aerospace and defense factory automation air and water quality environmental monitoring electronics design and development oceanographic research deepwater oil and gas exploration and production medical imaging and pharmaceutical research.

We are looking for individuals who thrive on making an impact and want the excitement of being on a team that wins.

Job Description

Teledyne LeCroy is a global leader in high-performance oscilloscopes protocol analyzers and signal integrity test solutions. For over 50 years our engineering teams have designed cutting-edge test and measurement equipment that shapes the future of electronics.

Our Frontline product family stands as the industry-standard validation platform for wireless technologies. Industry giants rely on Frontline hardwaresuch as the X500e and the flagship Frontline X700 analyzerto test and debug Bluetooth Wi-Fi 7 and IoT ecosystems. Joining Teledyne LeCroy means collaborating within an agile tech-focused culture to develop the crucial tools driving tomorrows connected world.

The Logic Lead drives the architectural design and FPGA implementation of next-generation wireless protocol analyzers. You will lead the development of digital logic on high-end FPGAs to capture demodulate and process high-speed RF signals for Bluetooth and other wireless standards.

Key Responsibilities:

Architecture & Design

• Define FPGA architecture for protocol filtering deep packet inspection and capture engines.
• Design RTL for hardware accelerators high-speed bus interfaces and external memory controllers.
• Implement demodulators and decoders for Bluetooth (LE Classic) and proprietary protocols.
• Optimize FPGA resources to maximize timing closure throughput and clock frequencies.

Leadership & Collaboration

• Lead engineers through the complete FPGA development lifecycle from concept to hardware timing closure.
• Collaborate closely with RF boards software drivers and system validation teams.
• Mentor junior and mid-level digital design and FPGA implementation engineers.
• Drive code reviews to maintain high-quality RTL and synthesis standards.

Verification & Testing

• Work with verification teams to build robust simulation and UVM testbench environments.
• Debug hardware issues on live FPGAs using Vivado ILA SignalTap or external logic analyzers.
• Support system integration to validate hardware co-design with software APIs.

Required Qualifications:

Technical Experience

• Education: Bachelors or Masters degree in Electrical or Computer Engineering.
• Experience: 8 years in digital RTL design with a strong focus on FPGA deployment.
• Languages: Expert-level mastery of SystemVerilog Verilog or VHDL.
• FPGA Platforms: Deep knowledge of high-performance AMD Xilinx (UltraScale Versal) or Intel Altera (Stratix/Agilex) architectures.

Domain Knowledge

• Wireless Protocols: Deep understanding of Bluetooth (BR/EDR/LE) physical and link layers.
• Interfaces: Experience with high-speed transceivers (GTY/GTY) PCIe USB 3.0 and DDR4/DDR5 memory interfaces.
• DSP Fundamentals: Familiarity with digital filters mixers and FFTs implemented in FPGA fabric.

Preferred Skills

• Experience building commercial test measurement or wireless sniffing equipment.
• Expertise in advanced timing closure techniques for high-utilization FPGA designs.
• Familiarity with Python C/C or MATLAB for hardware modeling and automated testing.

Teledyne and all of our employees are committed to conducting business with the highest ethical standards. We require all employees to comply with all applicable laws regulations rules and regulatory orders. Our reputation for honesty integrity and high ethics is as important to us as our reputation for making innovative sensing solutions.

.