(India) System IP Design Engineer

Tenstorrent is leading the industry on cutting-edge AI technology revolutionizing performance expectations ease of use and cost efficiency. With AI redefining the computing paradigm solutions must evolve to unify innovations in software models compilers platforms networking and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration curiosity and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Who You Are

• 510 years of experience in ASIC/SOC/IP design with hands-on experience in microarchitecture and RTL development
• Skilled in Verilog/SystemVerilog and comfortable working across design debug and analysis
• Design and develop microarchitectures for a set of highly configurable IPs
• Microarchitecture and RTL coding ensuring optimal performance power area
• Work with verification teams on assertions test plans debug coverage etc.
• Deep understanding of power management conceptsclocking reset DVFS and low-power modes
• Familiar with RISC-V or ARM-based SoCs and standard bus protocols (AXI AHB APB CHI)
• Awareness of functional safety (ISO 26262) practices in hardware design

What We Need

• Ability to own microarchitecture definition and RTL development of Power Management Subsystem/Interrupt Controllers/AXI Interconnect/Cache Controller
• Experience driving verification closure performance debug synthesis timing and power optimization
• Experience with large high-speed pipelined stateful designs and low power designs
• In-depth understanding of on-chip interconnects and NoCs
• Experience designing IP blocks for caches cache coherency memory subsystems interconnects and NoCs
• Familiarity with RAS designs QoS in fabrics PCIe/IO is a plus
• Excellent problem-solving skills and attention to detail
• Strong communication and collaboration skills
• Strong skills in LINT CDC/RDC and power intent checks
• Proficiency with DV and analysis tools like Verdi NCSIM and power estimation tools
• Hands-on experience in design-for-power debug and test methodologies

What You Will Learn

• Building power-efficient high-performance subsystems for advanced RISC-V/ARM architectures
• Cross-functional collaboration from concept to silicon bring-up
• Enhancing subsystem performance through innovative power performance and area optimizations
• Leadership and mentorship experience by guiding junior design engineers.

Tenstorrent offers a highly competitive compensation package and benefits and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws including those codified in the U.S. Export Administration Regulations (EAR) the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1 E1 and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information systems or technologies subject to these laws the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws any offer of employment will be rescinded.